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marvell. moving forward faster doc. no. mv-s104870-u0, rev. b february 27, 2008, preliminary c document classification: proprietary information cover 88sb2211 pci express-to-pci bridge datasheet
document conventions note: provides related information or information of special importance. caution: indicates potential damage to hardware or software, or loss of data. warning: indicates a risk of personal injury. document status doc status: preliminary te chnical publication: 0.xx for more information, visit our website at: www.marvell.com disclaimer no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including phot ocopying and recording, for any purpose, without the express written permission of marvell. marvell retains the right to make changes to this document at any time, with out notice. marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the impli ed warranties of merchantability or fitness for any particular purpose. further, marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situati on if any such products failed. do not use marvell products in these types of equipment or applications. with respect to the products described herein, the user or recipient, in the absence of appropriate u.s. government authorizati on, agrees: 1) not to re-export or release any such information consisting of technology, software or source code controlled for national s ecurity reasons by the u.s. export control regulations ("ear"), to a national of ear country groups d:1 or e:2; 2) not to export the direct product of such technology or such software, to ear country groups d:1 or e:2, if such technology o r software and direct products thereof are controlled for national security reasons by the ear; and, 3) in the case of technology controlled for national security reasons under the ear where the direct product of the technology is a complete plant or component of a plant, not to export to ear country groups d:1 or e:2 the direct product of the plant or major component thereof, if such direct produ ct is controlled for national security reasons by the ear, or is subject to controls under the u.s. munitions list ("usml"). at all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this doc ument in connection with their receipt of any such information. copyright ? 1999?2008. marvell international ltd. all rights reserved. marvell, the marvell logo, moving forward faster, alaska , fastwriter, datacom systems on silicon, libertas, link street, netgx, phyadvantage, prestera, raising the technology bar, the technology within, virtual cable tester, and yukon are registered trademarks of marvell. ants, anyvoltage, discovery, dsp switcher, feroceon, galnet, galtis, horizon, marvell makes it all possible, radlan, u nimac, and vct are trademarks of marvell. all other trademarks are the property of their respective owners. 88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 2 document classification: proprietary information february 27, 2008, preliminary
88sb2211 pci express-to-pci bridge datasheet copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 3 product overview the marvell ? 88sb2211 x1 pci express to 32-bit pci bridge connects legacy pci parallel bus devices to the new, advanced serial pci express interface. the 88sb2211 is a pci express-to-pci forward and reverse bridge. it is fully compliant with the pci-sig pci express-to-pci bridge specification. features ? marvell 88sb2211 x1 pci express to 32-bit pci bridge ? pci express-to-pci/pci-x bridge specification 1.0 compliant ? forward transparent bridge ? single pci express 1.0a x1 port ? single 32-bit pci2.3 33 mhz port ? single twsi port ? eight general purpose i/o pins ? single 3.3v power supply ? 64-bit addressing support ? vga and isa addressing support for legacy operation ? adjustable read prefetch algorithm ? access to all internal registers from the pci express port (in forward bridge mode only) ? ieee standard 1149.1 jtag interface ? pci express interface ? pci express base specifications, revision 1.0a compliant ? integrated pci express phy based on proven marvell serdes technology ? x1 link width, at 2.5 ghz signaling ? 100-mhz differential pci express reference clock generation, saving an external oscillator ? link crc ? lane polarity reversal support ? 128-byte maximum payload size (mps) ? single virtual channel (vc-0) ? advanced error reporting capability ? up to four master non-posted requests outstanding ? up to four target non-posted requests outstanding ? interrupt emulation message support ? error message support ? pci interface ? pci local bus specifications, revision 2.3 compliant ? 32-bit, 33 mhz operation ? 3.3v, 5v tolerant ? internal arbiter support for five external masters ? pci clock source for up to five external agents ? fast back-to-back capable ? up to four active target delayed reads ? power management ? advanced configuration power interface specifications (acpi) compliant ? supports all device power management states: d0, d1, d2, d3hot, and d3cold ? supports d3cold wake-up events upstream forwarding (pmen/waken) ? two wire serial interface (twsi) port ? optional eeprom initialization ? internal register access ? forward bridge applications ? atca pci express based platforms ? pci extension for server, desktop, and mobile motherboards ? expresscard and minicard applications ? split chassis platforms ? pci express docking stations ? reverse bridge applications ? picmg based platforms ? pci express extensions for pci platforms ? pc-card (pcmcia) and mini-pci applications ? lqfp128, 14 x 20 mm package, 0.5 mm pitch
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 4 document classification: proprietary information february 27, 2008, preliminary table of contents preface........................................................................................................................ .................................8 about this document............................................................................................................ ............................8 related documents...................... ........................................................................................ .............................8 document conventions ........................................................................................................... ..........................9 1 overview...................................................................................................................... ................. 10 2 pin information ............................................................................................................... ............. 11 2.1 summary list of functional pins..................... ........................................................................ ........................12 2.2 pci express interface pin assignments................ ....................................................................... ...................14 2.3 pci 32-bit interface pin assignments ................ ........................................................................ .....................15 2.4 reset pin assignments ....................................................................................................... ............................17 2.5 twsi interface pin assignments .............................................................................................. ......................17 2.6 jtag interface pin assignments .......................... .................................................................... ......................18 2.7 gpio interface pin assignments .............................................................................................. ......................19 2.8 analog interface pin assignments ............................................................................................ ......................19 2.9 power/ground pin assignments ........................... ..................................................................... .....................20 3 88sb2211 pinout ............................................................................................................... .......... 21 4 reset configuration ........................................................................................................... ......... 23 4.1 pins sample configuration.............................. ..................................................................... ...........................23 5 electrical specifications (pre liminary) ...................................................................................... 2 7 5.1 absolute maximum ratings ......... ........................................................................................... ........................27 5.2 recommended operating conditions ............. .............. .............. .............. .............. ........... ............ .................28 5.3 power dissipation ........................................ ................................................................... ................................29 5.4 current consumption ................................... ...................................................................... .............................30 5.5 dc electrical specifications ................................................................................................ ............................31 5.6 ac electrical specifications ................................................................................................ ............................32 5.7 differential interface electrical characteristics ........................................................................... .....................41 6 thermal data.................................................................................................................. .............. 44 7 package mechanical information ............................................................................................... 4 5 8 part order numbering/package marking .............. .................................................................... 47 8.1 part order numbering ........................................................................................................ .............................47 8.2 package marking ............................................................................................................. ...............................48
table of contents copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 5 a 88sb2211 register set......................................................................................................... ....... 55 a.1 registers overview .......................................................................................................... .............................. 55 a.2 register description ........................................................................................................ ............................... 55 b revision history .............................................................................................................. ..........142
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 6 document classification: proprietary information february 27, 2008, preliminary list of tables table 1: pin assignment table conventions ................... .................................................................... ...........12 table 2: functional pin list summary ............................................................................................ ................12 table 3: pci express interface pin a ssignments .................................................................................. .........14 table 4: pci 32-bit bus interface pin assignments ...... ......................................................................... .........15 table 5: reset pin assignments.............................. .................................................................... ...................17 table 6: twsi interface pin assignments ......................................................................................... .............17 table 7: jtag pin assignments ................................................................................................... ..................18 table 8: gpio interface pin assignments ......................................................................................... .............19 table 9: analog interface pin assign ments ....................................................................................... .............19 table 10: power/ground interface pin assignments ......... ....................................................................... ........20 table 11: 128 lqfp pinout pin list by pin number................................................................................ .........22 table 12: reset configuration ................................................................................................... .......................23 table 13: absolute maximum ratings .............................................................................................. ................27 table 14: recommended operating cond itions.......... .............. .............. .............. ............ ........... ........... .........28 table 15: power dissipation ................................ ..................................................................... ........................29 table 16: current consumption.............................. ..................................................................... .....................30 table 19: reference clock ac timing specifications .... .......................................................................... ........32 table 21: pci interface measurement condition parameters ........................................................................ ..35 table 25: pci express interface spread spectrum requirem ents...................................................................4 1 table 29: standard register field type codes........... ......................................................................... ............55 table 30: register map table for the forward bridge mode configuration registers .....................................57 table 76: register map table for the reverse bridge mo de configuration registers .....................................98 table 125: revision history ..................................................................................................... .........................142
list of figures copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 7 list of figures figure 1: 88sb2211 interface pin logic diagram ............ .............. .............. .............. .............. ............. ..........11 figure 2: 128 lqfp pinout (top view) ........................................................................................... ................21 figure 3: tval (max) rising edge test load ............ .............. .............. .............. ........... ........... .......... .............34 figure 4: tval (max) falling edge test load .............. .............. .............. .............. .............. ............... ..............34 figure 5: tval (min) test load & output slew rate test load ..................................................................... ..34 figure 6: pci interface clock waveform .......................................................................................... ...............35 figure 7: pci interface output timing measurement condi tions .............. .............. .............. .............. ............ 35 figure 8: pci interface input timing measurement condit ions ..................................................................... ..36 figure 9: twsi test circuit..................................................................................................... .........................37 figure 10: twsi output delay ac timing diagram......... ......................................................................... .........38 figure 11: twsi input ac timing di agram ............. .............. .............. .............. ........... ........... ............ ..............38 figure 12: jtag interface test circuit .......................................................................................... ....................39 figure 13: jtag interface output delay ac timing diagr am ........................................................................ ...40 figure 14: jtag interface input ac timing diagram ...... .............. .............. ........... ............ ........... ........... .........40 figure 15: pci express interface test circuit.......... ......................................................................... .................43 figure 16: 128-pin lqfp package diagr am ............. .............. .............. .............. ........... ........... ........... ............46 figure 17: sample part number ................................................................................................... .....................47
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 8 document classification: proprietary information february 27, 2008, preliminary preface about this document this datasheet provides the hardware specificat ions for the 88sb2211 pci express-to-pci bridge, including detailed pin information, configuration se ttings, electrical charac teristics, and physical specifications. it also provides detailed definiti ons of the registers im plemented in the device. in this document the 88sb2211 is often referred to as the ?device?. related documents ? 88sb2211 hardware design guidelines , document number mv-s300975-00 1 . ? pci local bus specification , revision 2.3 ? pci express base specification , revision 1.0a ? pci express to pci/pci-x bridge specification , revision 1.0 1. contact your local marvell ? sales representative for information about receiving this document.
preface document conventions copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 9 document conventions the following conventions are followed in this document: signal range a signal name followed by a range enclosed in brackets represents a range of logically related signals. the first number in the range indicates the most significant bit (msb) and the last number indicates the least significant bit (lsb). example: db_addr[12:0] active low signals # an n letter at the end of a signal name indicates that the signal?s active state occurs when voltage is low. example: intn state names state names are indicated in italic font. example: linkfail register naming conventions register field names are indicated by angle brackets. example: register field bits are enclosed in brackets. example: field [1:0] register addresses are represented in hexadecimal format. example: 0x0 reserved: the contents of the register are reserved for internal use only or for future use. a lowercase in angle brackets in a register indicates that there are multiple registers with this name. example: multicast configuration register reset values reset values have the following meanings: 0 = bit clear 1 = bit set abbreviations gb: gigabit gb: gigabyte kb: kilobit kb: kilobyte mb: megabit mb: megabyte numbering conventions unless otherwise indicated, all numbers in this document are decimal (base 10). an 0x prefix indicates a hexadecimal number. an 0b prefix indicates a binary number.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 10 document classification: proprietary information february 27, 2008, preliminary 1 overview the marvell ? 88sb2211 is a pci express-to-pci bridge that connects legacy pci parallel bus devices to the new advanced serial pci express interface. the 88sb2211 can also operate as a reverse bridge (pci-to-pci express), enabling con nection of pci express devices to the legacy pci bus. the 88sb2211 device is fully compliant with the pci express to pci/pci- x bridge specification , revision 1.0, and supports a transparent forward or reverse bridging scheme. it is a single function bridge with a single pci express virtual channel (v c-0). it also supports the standard pci-to-pci bridge programming model. the pci express port is fully compliant with the pci express base specification , revision 1.0a. it supports an x1 link operation, allowing simult aneous 250 mbps throughput in the upstream and downstream directions. the pci express port contai ns an integrated pci express phy, based on proven marvell serdes technology. for both down stream and upstream traffic, the 88sb2211 supports up to four outstanding non-posted requests . it supports a maximum payload size (mps) of 128 bytes, advanced error reporting (aer) capability , lane polarity inversion for easy board routing, and advanced pci express po wer management (pm) features. the pci port is 32 bits wide and operates at 33 mhz. it is fully compliant with pci local bus specification , revision 2.3. the 88sb2211 provides an inte rnal arbiter and buffered clock outputs for up to five subordinate pci devices. it supports 64-bit addressing, vga and isa addressing for legacy operation, and a tunable prefetch algorithm, which is useful for system throughput optimization. power management (pm) features include all convent ional pci d-states (software controlled), and pci express active state link pm mechanisms (hardware controlled). pme and wake protocols are also supported, ena bling the host system to furt her reduce power consumption. the 88sb2211 also contains a singl e twsi port for optio nal initialization, a single ieee standard 1149.1 jtag port for testability, and eight gene ral purpose i/o pins (gpios) for further system customization. the 88sb2211 can operate from a si ngle 3.3v power rail, to reduce system cost. this is achieved by various on die regulators (odrs) embedded in the device. to further optimize the power consumption, the odrs can be bypassed.
pin information copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 11 2 pin information the 88sb2211 is available in a 128-pin, lqfp package. figure 1 is the pin logic diagram for the device. figure 1: 88sb2211 interface pin logic diagram 88sb2211 gpio pci pci express jtag twsi power/ground pci_cben[3:0] pci_devseln pci_framen pci_gnt1-4n pci_intan pci_intbn pci_intcn pci_intdn pci_irdyn pci_par pci_perrn pci_req1-4n pci_stopn pci_serrn pci_trdyn pci_vio pci_cal pci_m66en pci_lockn pci_pmen pci_clk_out[5:1] pci_clk_out[0]/ pci_idseln pci_pad[31:0] analog vdd_io vdd_odr_core_b vdd_core odr_core_dis vss pll_avdd pll_avss vdd_odr_core_t jt_tck jt_trstn jt_tms jt_tdo jt_tdi xtal_in xtal_out ana_iset reset pci_gnt0n pci_req0n pex_clk_n pex_clk_p pex_rx_p pex_rx_n pex_tx_p pex_tx_n pex_iset pex_avdd pex_avddh pex_avddl pex_avss waken rst_inn rst_outn tw_sda tw_sck gpio[7:0] pci_clk_in
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 12 document classification: proprietary information february 27, 2008, preliminary 2.1 summary list of functional pins table 1 indicates the conventions used to identif y i/o or o type pins and their pad type. table 2 lists the pin count for each interface in the lqfp package. table 1: pin assignment table conventions abbreviation description i input ooutput i/o input/output t/s tri-state pin s/t/s sustained tri-state pin the pin is driven to its inactive value for one cycle before float. a pull-up is required to sustain the inactive value. o/d open drain pin the pin allows multiple drivers simultaneously (wire-or connection). a pull-up is required to sustain the inactive value. cml current mode logic analog analog supply/signal power vdd power supply gnd ground supply pci ? pci pad 3.3v according to the pci standard ? 5v tolerant hcsl high-speed current steering logic calib i/o calibration pin table 2: functional pin list summary interface prefix count lqfp package pci express pex_ 12 pci pci_ 70 reset rst_ 2 twsi tw_ 2 jtag jt_ 5 gpio gpio 8 vdd_io - 16 vdd_core - 2
pin information summary list of functional pins copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 13 vdd_odr_core_t - 1 vdd_odr_core_b - 1 odr_core_dis - 1 pll_avdd - 1 pll_avss - 1 analog - 3 ground (vss) - 3 nc (not connected) - 0 to ta l 1 2 8 table 2: functional pin list summary (continued) interface prefix count lqfp package
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 14 document classification: proprietary information february 27, 2008, preliminary 2.2 pci express interface pin assignments table 3: pci express interface pin assignments pin name i/o / pin type description pex_clk_p pex_clk_n i/o hscl pci express reference clock differential pair of pci express 100 mhz reference clock. the pci express clock direction is determined according to the reset strapping (see clock mode select in table 12, reset configuration, on page 23 ). pex_rx_p pex_rx_n i cml pci express receive lane differential pair of pci express receive data. pex_tx_p pex_tx_n o cml pci express transmit lane differential pair of pci express transmit data. pex_iset o analog pci express current reference connect to an external 6.04+/-1% k waken o/d i/o pci pci express wake (wake#) when working in forward bridge mode, this signal is an output. when working in reverse bridge mode, this signal is an input.
pin information pci 32-bit interface pin assignments copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 15 2.3 pci 32-bit interface pin assignments table 4: pci 32-bit bus interface pin assignments pin name i/o / pin type description pci_vio i pci pci voltage i/o clamping reference voltage for pci (3.3v or 5v). pci_m66en i pci pci 66 mhz enable the 88sb2211 does not support 66 mhz pc i. therefore, pull this pin down to 0. pci_pad[31:0] t/s i/o pci pci address/data 32-bit pci multiplexed address/data bus. driven by the transaction master during the address phase and the write data phase. driven by the target device during the read data phase. pci_cben[3:0] t/s i/o pci pci command/byte enable a multiplexed command/byte-enable bus, driven by the transaction master. contains the command during the address phase, and the byte-enable during data phase. pci_par t/s i/o pci pci parity even parity is calculated for pci_pad[31:0] and pci_cben[3:0]. driven by the transaction master for the address phase and the write data phase. this pin is driven by the target for the read data phase. pci_framen s/t/s i/o pci pci frame asserted by the transaction master to indicate the beginning of a transaction. the master de-asserts pci_framen to indicate that the next data phase is the final data phase transaction. pci_devseln s/t/s i/o pci pci device select asserted by the target of the current access. as a master, the target device is expected to assert pci_devseln within five bus cycles. otherwise, it aborts the cycle. as a target, pci_devseln is asserted at a medium speed; two cycles after the assertion of pci_framen. pci_irdyn s/t/s i/o pci pci initiator ready asserted by the transaction master to in dicate it is ready to complete the current data phase of the transaction. a data phase is completed when both pci_trdyn and pci_irdyn are asserted. pci_trdyn s/t/s i/o pci pci target ready asserted by the target to indicate it is ready to complete the current data phase of the transaction. a data phase is completed when both pci_trdyn and pci_irdyn are asserted. pci_stopn s/t/s i/o pci pci stop asserted by target to indicate transaction termination. used by a target device to generate a retry, disconnect, or target abort termination signal.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 16 document classification: proprietary information february 27, 2008, preliminary pci_req0n pci_req1n pci_req2n pci_req3n pci_req4n i/o i i i i pci pci bus request when the internal pci arbiter is used, these pins are used as the request inputs from the external agents. when an external arbiter is used, pci_req0n is used as the reqn output of the bridge. pci_gnt0n pci_gnt1n pci_gnt2n pci_gnt3n pci_gnt4n t/s i/o t/s o t/s o t/s o t/s o pci pci bus grant when the internal pci arbiter is used, these pins are used as the grant outputs for the external agents. when an external arbiter is used, pci_gnt0n is used as the gntn input of the bridge. pci_perrn s/t/s i/o pci pci parity error asserted when a data parity error is detected. asserted by a target device in response to bad address or write data parity, or by the master device in response to bad read data parity. pci_serrn o/d i/o pci pci system error asserted when a system error is detected. pci_lockn i/o pci pci lock pci_pmen o/d i/o pci pci power management event pci_clk_out[0] pci_idseln o i pci pci clock output/pci idsel note: in reverse bridge mode, pci_clk_out[0] acts as the device pci_idseln pin (input). pci_clk_out[5:1] o pci pci clock output pci_clk_in i pci pci clock input pci_intan o/d i/o pci pci interrupt request a pci_intbn o/d i/o pci pci interrupt request b pci_intcn o/d i/o pci pci interrupt request c pci_intdn o/d i/o pci pci interrupt request d pci_cal i calib pci pads calibration input (refer to the 88sb2211 hardware design guidelines for a description of the pin connectivity). table 4: pci 32-bit bus interf ace pin assignments (continued) pin name i/o / pin type description
pin information reset pin assignments copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 17 2.4 reset pin assignments 2.5 twsi interface pin assignments table 5: reset pin assignments pin name i/o / pin type description rst_inn i pci reset in ? when working in forward bridge mode, this is the pci express reset input signal (perst#). ? when working in reverse bridge mode, this is the pci reset input signal (prst#). rst_outn o pci reset out ? when working in forward bridge mode, this is the pci reset output signal. ? when working in reverse bridge mode, this is the pci express reset output signal. table 6: twsi interface pin assignments pin name i/o / pin type description tw_sda o/d i/o pci twsi port serial data address or write data driven by the twsi master or read response data driven by the twsi slave. note: the 88sb2211 slave address is 7'h2f (7'b0101111). since this pin contains and internal pull-up, it can be left unconnected when not used. if used, it requires an external pull-up. tw_scl o/d i/o pci twsi port serial clock serves as output when acting as a twsi master. serves as input when acting as a twsi slave. note: since this pin contains and internal pull-up, it can be left unconnected when not used. if used, it requires an external pull-up.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 18 document classification: proprietary information february 27, 2008, preliminary 2.6 jtag interface pin assignments table 7: jtag pin assignments pin name i/o / pin type description jt_tck i pci jtag clock clock input for the jtag controller. note: this pin is internally pulled down to 0. jt_trstn i pci jtag reset when asserted, resets the jtag controller. note: this pin is internally pulled down to 0. 1 jt_tms i pci core jtag mode select controls the core jtag controller state. sampled with the rising edge of jt_tck. note: this pin is internally pulled up to 1. jt_tdo o pci jtag data out driven on the falling edge of jt_tck. jt_tdi i pci jtag data in jtag serial data input. sampled with the jt_tck rising edge. note: this pin is internally pulled up to 1. 1. if this pull-down conflicts with other dev ices, the jtag tool must not use this signal. this signal is not mandatory for the jtag interface, since the tap can be reset by driv ing the jt_tms signal high for five jt_tck cycles.
pin information gpio interface pin assignments copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 19 2.7 gpio interface pin assignments 2.8 analog interface pin assignments table 8: gpio interface pin assignments pin name i/o / pin type description gpio[7:0] t/s i/o pci general purpose pin various functions table 9: analog interface pin assignments pin name i/o / pin type description xtal_in i analog crystal input/reference clock input 25 mhz. when using a crystal, this pin is used as the xtal_in input. note: when not using crystal, this pin must be pulled down to 0. xtal_out o analog crystal output note: leave unconnected if a crystal is not used. ana_iset o analog current reference connect to an external 6.04 k
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 20 document classification: proprietary information february 27, 2008, preliminary 2.9 power/ground pin assignments table 10: power/ground interface pin assignments pin name i/o / pin type description vdd_io i/o power 3.3v power supply for all in terfaces, excluding pci express interface. vdd_odr_ core_t i power 3.3v filtered power supply for the core voltage (1.2v) odr. vdd_odr_ core_b i power 3.3v filtered power supply for the core voltage (1.2v) odr. vdd_core i power connect these pins to decoupling capacitors (0.1 f). note: when odr is bypassed (odr_core_dis = 1), these pins are the vdd_core 1.2v power supply. odr_core_dis i analog core voltage on-die-regulator control ? vss?core on-die-regulator enabled (default) ? 3.3v?core on-die-regula tor disabled (bypassed) vss i gnd ground pll_avdd i power pll 3.3v filtered power pll_avss i gnd pll ground
88sb2211 pinout copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 21 3 88sb2211 pinout this section provides the pin map and pinout table for the 88sb2211?128 lqfp. see 2 "pin information" on page 11 for a detailed description of the pin signals. figure 2: 128 lqfp pinout (top view) rst_inn tw_sda tw_scl pci_intan pci_intcn pci_intbn pci_intdn vss rst_outn vdd_io pci_clk_in vdd_io gpio[0] gpio[1] gpio[2] gpio[3] vdd_io pci_clk_out[5] pci_clk_out[4] pci_clk_out[3] vdd_io pci_clk_out[2] pci_clk_out[1] pci_clk_out[0] * vdd_odr_core_t odr_core_dis pci_req1n pci_req0n vdd_io pci_gnt0n pci_req2n pci_gnt2n pci_req4n pci_gnt1n pci_req3n pci_gnt4n pci_gnt3n vdd_io ## jt_tms 103 64 pci_ pmen jt_tdi 104 63 gpio[5] vdd_io 105 62 pci_ v io jt_tck 106 61 pci_pad[30] jt_trstn 107 60 pci_pad[28] waken 108 59 gpio[4] jt_tdo 109 58 vdd_io v dd_core 110 57 pci_ ca l xtal_in 111 56 pci_pad[29] xtal_out 112 55 pci_pad[31] vss 113 54 pci_pad[27] pll_avdd 114 53 pci_pad[26] pll_avss 115 52 pci_pad[25] ana_iset 116 51 pci_ cben [ 3 ] vss 117 50 v dd_core pex_clk_p 118 49 vdd_io pex_clk_n 119 48 pci_pad[19] pex_ a v ddl 120 47 pci_pad[23] pex_ rx_ p 121 46 pci_pad[17] pex_ rx_ n 122 45 pci_pad[24] pex_ a v ddh 123 44 pci_pad[21] pex_ a v dd 124 43 pci_ cben [ 2 ] pex_ tx_ p 125 42 vdd_io pex_ tx_ n 126 41 pci_pad[20] pex_av ss 127 40 pci_pad[22] pex_ iset 128 39 pci_pad[16] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 pci_pad[1] . pci_pad[0] . pci_pad[4] . vdd_io . pci_pad[3] . pci_pad[2] . pci_cben[0] vdd_io . pci_pad[5] . pci_pad[6] . pci_pad[7] . pci_pad[11] . pci_pad[9] . pci_pad[8] . vdd_io . pci_pad[10] . pci_m66en pci_pad[12] . pci_pad[14] . vdd_odr_core_b vdd_io . pci_pad[13] . pci_cben[1] pci_serrn pci_pad[15] . vdd_io . pci_lockn pci_perrn pci_par . pci_trdyn pci_devseln pci_stopn vdd_io . gpio[6] . pci_irdyn pci_framen gpio[7] . pci_pad[18] . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 88sb2211 top view 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 epad - vss 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 * in reverse bridge mode, pin 79 acts as the device pci_idseln pin (input).
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 22 document classification: proprietary information february 27, 2008, preliminary table 11: 128 lqfp pinout pin list by pin number * in reverse bridge mode, pin 79 acts as the device pci_idseln pin (input). pin # pin nam e pin # pin nam e pin # pin nam e 1 pci_pad[1] 44 pci_pad[21] 87 gpio[3] 2 pci_pad[0] 45 pci_pad[24] 88 gpio[2] 3 pci_pad[4] 46 pci_pad[17] 89 gpio[1] 4 vdd_io 47 pci_pad[23] 90 gpio[0] 5 pci_pad[3] 48 pci_pad[19] 91 vdd_io 6 pci_pad[2] 49 vdd_io 92 pci_clk_in 7 pci_cben[0] 50 vdd_core 93 vdd_io 8 vdd_io 51 pci_cben[3] 94 rst_outn 9 pci_pad[5] 52 pci_pad[25] 95 vss 10 pci_pa d[6] 53 pci_pa d[26] 96 pci_intdn 11 pci_pad[7] 54 pci_pad[27] 97 pci_intbn 12 pci_pad[11] 55 pci_pad[31] 98 pci_intcn 13 pci_pad[9] 56 pci_pad[29] 99 pci_intan 14 pci_pad[8] 57 pci_cal 100 tw_scl 15 vdd_io 58 vdd_io 101 tw_sda 16 pci_pad[10] 59 gpio[4] 102 rst_inn 17 pci_m66en 60 pci_pad[28] 103 jt_tms 18 pci_pad[12] 61 pci_pad[30] 104 jt_tdi 19 pci_pad[14] 62 pci_vio 105 vdd_io 20 vdd_odr_core_b 63 gpio[5] 106 jt_tck 2 1 v dd_ io 6 4 pci_ pmen 1 0 7 jt_ trstn 22 pci_pad[13] 65 vdd_io 108 waken 23 pci_cben[1] 66 pci_gnt3n 109 jt_tdo 24 pci_serrn 67 pci_gnt4n 110 vdd_core 25 pci_pad[15] 68 pci_req3n 111 xtal_in 26 vdd_io 69 pci_gnt1n 112 xtal_out 27 pci_lockn 70 pci_req4n 113 vss 28 pci_perrn 71 pci_gnt2n 114 pll_avdd 29 pci_par 72 pci_req2n 115 pll_avss 30 pci_trdy n 73 pci_gnt0n 116 a na _iset 31 pci_devseln 74 vdd_io 117 vss 32 pci_stopn 75 pci_req0n 118 pex_clk_p 33 vdd_io 76 pci_req1n 119 pex_clk_n 34 gpio[6] 77 odr_core_dis 120 pex_avddl 35 pci_irdyn 78 vdd_odr_core_t 121 pex_rx_p 36 pci_framen 79 pci_clk_out[0] * 122 pex_rx_n 37 gpio[7] 80 pci_clk_out[1] 123 pex_avddh 38 pci_pad[18] 81 pci_clk_out[2] 124 pex_avdd 39 pci_pad[16] 82 vdd_io 125 pex_tx_p 40 pci_pad[22] 83 pci_clk_out[3] 126 pex_tx_n 41 pci_pad[20] 84 pci_clk_out[4] 127 pex_avss 42 vdd_io 85 pci_clk_out[5] 128 pex_iset 43 pci_cben[2] 86 vdd_io
reset configuration pins sample configuration copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 23 4 reset configuration 4.1 pins sample configuration unless specifically noted, all reset sampled pins are sampled upon de-assertion of rst_inn. table 12 describes the reset pins configuration. table 12: reset configuration pin configuration function pci_m66en pci 66 mhz enable 0 = disabled 1 = enabled sampled upon de-assertion of pci_prstn. note: since the 88sb2211 does not support pci 66 mhz, this pin must be pulled down to 0. pci_reqn[0] pci slot 0 enable enables both pci_clk_out[0] output and pci_reqn[0] input. when disabled, the clock output is forced to zero, and the request input is internally masked. 0 = disabled 1 = enabled note: internally pulled up to 1. when working with an external arbiter, pci_clk_out[0] is enabled by default, since this signal functions as pci_req output and the pci specification requires a pull up on this signal. shutting down pci_clk_out[0] is only supported via the table 52, forward bridge pci clock output control register, on page 81 or table 101, reverse bridge pci clock output control register, on page 124 access. pci_reqn[1] pci slot 1 enable enables both pci_clk_out[1] output and pci_reqn[1] input. when disabled, the clock output is forced to zero, and the request input is internally masked. 0 = disabled 1 = enabled note: internally pulled up to 1. when working with the internal arbiter providing req/gnt coupled to slot 1, this signal must be pulled up, according to the pci specification. in this case, shutting down pci_clk_out[1] is only supported via the table 52, forward bridge pci clock output control register, on page 81 or table 101, reverse bridge pci clock output control register, on page 124 access.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 24 document classification: proprietary information february 27, 2008, preliminary pci_reqn[2] pci slot 2 enable enables both pci_clk_out[2] output and pci_reqn[2] input. when disabled, the clock output is forced to zero, and the request input is masked internally. 0 = disabled 1 = enabled note: internally pulled up to 1. when working with the internal arbiter providing req/gnt coupled to slot 2, this signal must be pulled up according to the pci specification. shutting down pci_clk_out[2] in this case is only supported via table 52, forward bridge pci clock output control register, on page 81 or table 101, reverse bridge pci clock output control register, on page 124 access. pci_reqn[3] pci slot 3 enable enables both pci_clk_out[3] output and pci_reqn[3] input. when disabled, the clock output is forced to zero, and the request input is internally masked. 0 = disabled 1 = enabled note: internally pulled up to 1. when working with the internal arbiter providing req/gnt coupled to slot 3, this signal must be pulled up according to the pci specification. in this case, shutting down pci_clk_out[3] is only supported via table 52, forward bridge pci clock output control register, on page 81 or table 101, reverse bridge pci clock output control register, on page 124 access. pci_reqn[4] pci slot 4 enable enables both pci_clk_out[4] output and pci_reqn[4] input. when disabled, the clock output is forced to 0, and the request input is masked internally. 0 = disabled 1 = enabled note: internally pulled up to 1. when working with the internal arbiter providing req/gnt coupled to slot 4, this signal must be pulled up, according to the pci specification. in this case, shutting down pci_clk_out[4] is only supported via table 52, forward bridge pci clock output control register, on page 81 or table 101, reverse bridge pci clock output control register, on page 124 access. gpio[0] serial rom initialization 0 = disabled 1 = enabled note: internally pulled down to 0. table 12: reset configuration (continued) pin configuration function
reset configuration pins sample configuration copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 25 gpio[1] pci express reference clock source select 0 = 100 mhz differential reference clock 1 = 125 mhz single-ended reference clock note: internally pulled down to 0. refer to clock mode select reset configuration for additional information on the reference clock options. gpio[2] 1.5v on die regulator disable 0 = 1.5v odr enabled. 1 = 1.5v odr disabled. 1.5v fed directly from the board. note: internally pulled down to 0. gpio[3] 2.5v on die regulator disable 0 = 2.5v odr enabled. 1 = 2.5v odr disabled. 2.5v fed directly from the board. note: internally pulled down to 0. pci_gntn[1] internal pci arbiter enable 0 = disabled 1 = enabled note: internally pulled up to 1. pci_gntn[3:2] clock mode select 0 = xtal clock source mode reference clock to the pll is xtal_in (25 mhz). pex_clk_n and pex_clk_p are inputs. 1 = xtal clock source mode (pci express clock internal generation) reference clock to the pll is xtal_in (25 mhz). pex_clk_n and pex_clk_p are outputs. note: when working in this mode, only pci agents 0, 1, and 2 are supported in the device internal arbiter. 2 = pci clock source mode reference clock to the pll is pci_clk_in (applicable only when the pci clock period is exactly 30 ns). pex_clk_n and pex_clk_p are outputs. 3 = pci express clock source mode reference clock to the pll are pex_clk_n and pex_clk_p. (inputs) see the 88sb2211 hardware design guidelines for additional information about the clock modes. note: pci_gntn[3] and pci_gntn[2] are internally pulled up to 1. pci_gntn[4] bridge mode select 0 = reverse bridge mode?the host is on pci side. 1 = forward bridge mode?the host is on pci express side. note: internally pulled up to 1. table 12: reset configuration (continued) pin configuration function
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 26 document classification: proprietary information february 27, 2008, preliminary note pci_clk_out[5] is automatically disabled when all five pci_clk_out[4:0] pins are disabled.
electrical specifications (preliminary) absolute maximum ratings copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 27 5 electrical specifications (preliminary) the numbers specified in this section are preliminary and subject to change. 5.1 absolute maximum ratings table 13: absolute maximum ratings parameter min max units comments vdd_core -0.5 1.5 v core voltage vdd_odr_core_b -0.5 4.0 v input voltage for: core odr vdd_odr_core_t -0.5 4.0 v input voltage for: core odr odr_core_dis -0.5 4.0 v core odr disable signal pll_avdd -0.5 4.0 v analog supply for the internal pll vdd_io 1 -0.5 4.0 v i/o voltage for: pci, twsi and jtag interfaces pci_vio 1 -0.5 6.0 v i/o voltage for: pci interface pex_avddh -0.5 4.0 v high voltage for: pci express interface pex_avdd -0.5 3.0 v analog voltage for: pci express interface when bypassing 2.5v odr pex_avddl -0.5 1.8 v analog voltage for: pci express interface when bypassing 1.5v odr tc -40 125 c case temperature tstg -40 125 c storage temperature 1. input voltage must not exceed the respective interface supply voltage more than 0.7 v. caution ? exposure to conditions at or beyond the maximum rating may damage the device. ? operation beyond the recomme nded operating conditions ( ta b l e 1 4 ) is neither recommended nor guaranteed. note before designing a system, it is recomme nded that you read application note an-63: thermal management for marvell ? technology products . this application note presents basic concepts of thermal mana gement for integrated circuits (ics) and includes guidelines to ensure optimal operating conditions for marvell technology's products.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 28 document classification: proprietary information february 27, 2008, preliminary 5.2 recommended operating conditions table 14: recommended operating conditions parameter min typ max units comments vdd_core 1.1 1.2 1.3 v core voltage when bypassing the 3.3v core odr vdd_odr_core_b 3 3.3 3.6 v input voltage for: core odr vdd_odr_core_t 3 3.3 3.6 v input voltage for: core odr pll_avdd 3 3.3 3.6 v analog supply for the internal pll vdd_io 3 3.3 3.6 v i/o voltage for: pci, twsi, and jtag interfaces pci_vio 4.75 5 5.25 v i/o voltage for: pci interface 33.33.6v pex_avddh 3 3.3 3.6 v high voltage for: pci express interface pex_avdd 2.375 2.5 2.625 v analog voltage for: pci express interface when bypassing 2.5v odr pex_avddl 1.425 1.5 1.575 v analog voltage for: pci express interface when bypassing 1.5v odr tj 0 125 c junction temperature caution operation beyond the recommended operat ing conditions is neither recommended nor guaranteed.
electrical specifications (preliminary) power dissipation copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 29 5.3 power dissipation note: typ power is the maximal powe r measured at typical conditions. table 15: power dissipation interface symbol test conditions typ max units power dissipation (utilizing all odrs) pd 700 820 mw power dissipation (odrs) pd 630 mw power dissipation (no odrs utilization) pd 500 mw
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 30 document classification: proprietary information february 27, 2008, preliminary 5.4 current consumption notes: 1. current in ma is calculated using maximum recommended vddio specif ication for each power rail. 2. all output clocks toggling at their specified rate. 3. maximum drawn current from the power supply. 4. when the core odr is not bypassed, the core current is drawn from both vdd_odr_core_b and vdd_odr_core_t. table 16: current consumption interface symbol test conditions max units pci (33 mhz 32-bit) interface i pci 25 pf load 100 ma pci express interface (with odr disabled) i pex_avddh avddh @ 3.3v 0 ma i pex_avdd avdd @ 2.5v 20 ma i pex_avddl avddl @ 1.5v 40 ma pci express interface (with odr enabled) i pex_avddh avddh @ 3.3v 65 ma i pex_avdd avdd @ 2.5v 0 ma i pex_avddl avddl @ 1.5v 0 ma core vdd_core, vdd_odr_core_b, or vdd_odr_core_t i vdd_core 80 ma
dc electrical specifications copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 31 5.5 dc electrical specifications 5.5.1 pci, jtag, and gpio 3. 3v interfaces dc electrical specifications the values in ta b l e 1 7 also apply to the odr_core_dis signal. table 17: pci, jtag, and gpio 3.3v interface dc electrical specifications 5.5.2 two-wire serial interface (twsi) 3.3v dc electrical specifications table 18: twsi interface 3.3v dc electrical specifications parameter symbol test condition min typ max units notes input low level vil -0.5 0.3*vddio v - input high level vih 0.5*vddio vio+0.5 v - output low level vol iol = 1.5 ma - 0.1*vddio v - output high level voh ioh = -0.5 ma 0.9*vddio - v - input leakage current iil 0 < vin < vddio -10 10 ua 1, 2 pin capacitance cpin 5 pf - no t e s : general comment: see the pin description section for internal pullup/pulldow n. 1. while i/o is in high-z. 2. this current does not include the current flow ing through the pullup/pulldow n resistor. parameter symbol test condition min typ max units notes input low level vil -0.5 0.3*vddio v - input high level vih 0.7*vddio vddio+0.5 v - output low level vol iol = 3 ma - 0.4 v - input leakage current iil 0 < vin < vddio -10 10 ua 1, 2 pin capacitance cpin 5 pf - no t e s : general comment: see the pin description section for internal pullup/pulldow n. 1. while i/o is in high-z. 2. this current does not include the current flow ing through the pullup/pulldow n resistor.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 32 document classification: proprietary information february 27, 2008, preliminary 5.6 ac electrical specifications see 5.7 "differential interface electrical characteristics" on page 41 for differential interface specifications. 5.6.1 reference clock ac timing specifications note: 1. slew rate is measured from 20% to 80% of the reference clock signal. table 19: reference clock ac timing specifications description symbol min max units notes xtal_in reference clock frequency f xtal_in 25 - 100 ppm 25 + 100 ppm mhz clock duty cycle dc xtal_in 40 60 % slew rate sr xtal_in 0.7 v/ns 1 pk-pk jitter jr xtal_in 200 ps
copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 33 5.6.2 pci interface ac timing 5.6.2.1 pci interface ac timing table table 20: pci interface ac timing table min max clock cycle time tcyc 30.0 - ns 1 clock high time thigh 11.0 - ns - clock low time tlow 11.0 - ns - clock slew rate - 1.0 4.0 v/ns 2 clock rising edge to signal valid delay for bused signals tval 2.0 11.0 ns 3, 4 clock rising edge to signal valid delay for point to point signals tval(ptp) 2.0 12.0 ns 3, 4 input setup time to clock rising edge for bused signals tsu 7.0 - ns 4, 6, 8 input setup time to clock rising edge for point to point signals tsu(ptp) 10, 12 - ns 4, 5, 6 input hold time from clock rising edge th 0.0 - ns 6 reset active time trst 1.0 - ms 7 output rise slew rate tr 1.0 4.0 v/ns 9 output fall slew rate tf 1.0 4.0 v/ns 9 no t e s : 1. the minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter. 2. this slew rate must be met across the minimum peak-to-peak portion of the clock w aveform as show n in the pci interface clock w aveform. 3. see the timing measurment conditions in the output timing measurement conditions figure. 4. point-to-point signals applies to reqn and gntn only. all other signals are bused. 5. gntn has a setup of 10 ns; reqn has a setup of 12 ns. 6. see the timing measurement conditions in the input timing measurement conditions figure. 7. rstn is asserted and deasserted asynchronously w ith respect to clock. 8. setup time applies only w hen the device is not driving the pin. devices cannot drive and receive signals at the same time. 9. the test load is specified in the tval (min) test load figure. no t e s description symbol units pci 33 mhz @ 3.3v
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 34 document classification: proprietary information february 27, 2008, preliminary 5.6.2.2 pci interface test circuit figure 3: tval (max) rising edge test load figure 4: tval (max) falling edge test load figure 5: tval (min) test load & output slew rate test load test point tval (max) low to high 10 pf 25 ohm 10 pf 25 ohm vcc test point tval (max) high to low tval (min) test point 10 pf 1 kilohm 1 kilohm vcc
copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 35 5.6.2.3 pci interface measu rement condition parameters table 21: pci interface measurement condition parameters 5.6.2.4 pci interface ac timing measurement waveforms figure 6: pci interface clock waveform figure 7: pci interface output timing measurement conditions symbol pci units notes vth 0.6 vcc v - vtl 0.2 vcc v - vtest 0.4 vcc v - vtrise 0.285 vcc v 1 vtf all 0.615 vcc v 1 output rise slew rate 0.3 vcc to 0.6 vcc v - output fall slew rate 0.6 vcc to 0.3 vcc v - input signal slew rate 1.5 v/ns - notes: 1. vtrise and vtfall are ref erence voltages f or timing def initions only. tcyc 0.6 vcc vih(min) vtest vil(max) thigh tlow 0.4 vcc peak to peak (minimum) clock output delay output delay tval tval vth vtl vtest vtfall vtrise (falling) (rising)
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 36 document classification: proprietary information february 27, 2008, preliminary figure 8: pci interface input timing measurement conditions clock input th vth vtl vtest vtest tsu inputs valid
copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 37 5.6.3 two-wire serial interface (twsi) ac timing 5.6.3.1 twsi ac timing table table 22: twsi ac timing table 5.6.3.2 twsi test circuit figure 9: twsi test circuit min max sck minimum low lev el w idth t low 4. 7 - us 1 sck minimum high level w idth thigh 4.0 - us 1 sda input setup time relative to sck rising edge tsu 250.0 - ns - sda input hold time relative to sck fa lling edge thd 0.0 - ns - sda and sck rise time tr - 1000.0 ns 1, 2 sda and sck fall time tf - 300.0 ns 1, 2 sda output delay relative to sck falling edge tov 0.0 4.0 us 1 no t e s : general comment: all values referred to vih(min) and vil(max) levels, unless otherw ise specified. 1. for all signals, the load is cl = 100 pf, and rl value can be 500 ohm to 8 kilohm. 2. rise time measured from vil(max) to vih(min), fall time measured from vih(min) to vil(max). no t e s 100 khz description symbol units cl rl vddio test point
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 38 document classification: proprietary information february 27, 2008, preliminary 5.6.3.3 twsi ac timing diagrams figure 10: twsi output delay ac timing diagram figure 11: twsi input ac timing diagram tov(min) sck sda vih(min) vil(max) vih(min) vil(max) tov(max) thigh tlow vih(min) vil(max) vih(min) vil(max) tsu tlow thigh sck sda thd
copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 39 5.6.4 jtag interface ac timing 5.6.4.1 jtag interface ac timing table table 23: jtag interface 5 mhz ac timing table 5.6.4.2 jtag interface test circuit figure 12: jtag interface test circuit min max jtclk frequency fck mhz - jtclk minimum pulse w idth tpw 0.40 0.60 tck - jtclk rise/fall slew rate sr/sf 0.50 - v/ns 2 jtrstn active time trst 1.0 - ms - tms, tdi input setup relative to jtclk rising edge tsetup 10.0 - ns - tms, tdi input hold relative to jtclk rising edge thold 75.0 - ns - jtclk f alling edge to tdo output delay tprop 1.0 20.0 ns 1 no t e s : general comment: all values w ere measured from vddio/2 to vddio/2, unless otherw ise specified. general comment: tck = 1/fck. 1. for tdo signal, the load is cl = 20 pf. 2. defined from vil to vih for rise time, and from vih to vil for fall time. 5.0 no t e s 5 mhz description symbol units cl test point
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 40 document classification: proprietary information february 27, 2008, preliminary 5.6.4.3 jtag interface ac timing diagrams figure 13: jtag interface output delay ac timing diagram figure 14: jtag interface input ac timing diagram jtck tdo tprop (min) tprop (max) vih vil thold tsetup jtck tms,tdi
differential interface electrical characteristics copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 41 5.7 differential interface electrical characteristics this section provides the reference clock, ac, and dc characteristics for the pci express interface. 5.7.1 differential interface re ference clock characteristics table 24: pci express interface differential reference clock characteristics pci express interface spread spectrum requirements table 25: pci express interface spread spectrum requirements description sym bol min max units notes input clock frequency fck mhz - input clock duty cycle dcrefclk 0.45 0.55 tck - input clock rise/fall time trrefclk 175.0 700.0 ps 1, 3 input clock rise/fall time variation dltrrefclk - 125.0 ps 1, 3 input high voltage vihrefclk 660.0 850.0 mv 1 input low voltage vilrefclk -150.0 50.0 mv 1 absolute crossing point voltage vcross 250.0 550.0 mv 1 variation of vcross over all rising clock edges vcrs_dlta - 140.0 mv 1 absolute maximum input voltage (overshoot) vmax - 1.15 v 1 absolute minimum input voltage (undershoot) vmin - -0.3 v 1 absolute differential clock period tperabs 9.872 - ns 2 differential clock cycle-to-cycle jitter tccjit - 125.0 ps - no t e s : general comment: the reference clock timings are based on 100 ohm test circuit. general comment: refer to the pci express card electromechanical specification, revision 1.0a, april 2003, section 2.6.3 for more information. 1. defined on a single ended signal. 2. including jitter and spread spectrum. 3. defined from 0.175v to 0.525v. 100.0 symbol min max units notes fmod 0.0 33.0 khz - fspread -0.5 0.0 % -
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 42 document classification: proprietary information february 27, 2008, preliminary 5.7.2 pci express interface electrical characteristics 5.7.2.1 pci express interface driver and receiver characteristics table 26: pci express interface driver and receiver characteristics description symbol min max units notes baud rate br gbps - unit interval ui ps - baud rate tolerance bppm -300.0 300.0 ppm 2 differential peak to peak output voltage vtxpp 0.8 1.2 v - minimum tx eye w idth ttxeye 0.7 - ui - differential return loss trldiff 12.0 - db 1 common mode return loss trlcm 6.0 - db 1 dc differential tx impedance ztxdiff 80.0 120.0 ohm - differential input peak to peak voltage vrxpp 0.175 1.2 v - minimum receiver eye w idth trxeye 0.4 - ui - dif f erential return loss rrldif f 15.0 - db 1 common mode return loss rrlcm 6.0 - db 1 dc differential rx impedance zrxdiff 80.0 120.0 ohm - dc common input impedance zrxcm 40.0 60.0 ohm - no t e s : general comment: for more information, refer to the pci express base specification, revision 1.0a, april, 2003. 1. defined from 50 mhz to 1.25 ghz. 2. does not account for ssc dictated variations. driver parameters receiver parameters 2.5 400.0
copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 43 5.7.2.2 pci express interface test circuit figure 15: pci express interface test circuit when measuring transmitter output parameters, c_tx is an optional portion of the test/measurement load. when used, the value of c_tx must be in the range of 75 nf to 200 nf. c_tx must not be used when the test/measurement load is placed in the receiver package reference plane. test points c_tx 50 ohm 50 ohm c_tx + - d+ d-
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 44 document classification: proprietary information february 27, 2008, preliminary 6 thermal data this section provides the package thermal data for the 88sb2211. this data is derived from simulations that were run according to the jedec standard. the thermal parameters are preliminary and subject to change. the documents listed below provide a basic under standing of thermal management of integrated circuits (ics) and guidelines to ensure optimal oper ating conditions for marvell products. before designing a system it is recommended to refer to these documents: ? application note, an-63 thermal management for selected marvell? products, document number mv-s300281-00 1 ? white paper, thetajc, thetaja, and temperature calculations, document number mv-s700019-00 1 table 27 shows the lqfp package thermal data for the 88sb2211. the simulation was done according to the jedec standard. 1. contact your local marvell ? sales representative for information about receiving this document. table 27: 128 lqfp package thermal data parameter definition airflow value 0 m / s 1 m / s 2 m/s
package mechanical information copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 45 7 package mechanical information this section provides the package mechanical information for the 88sb2211 128-pin lqfp package.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 46 document classification: proprietary information february 27, 2008, preliminary figure 16: 128-pin lqfp package diagram
part order numberi ng/package marking part order numbering copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 47 8 part order numbering/package marking 8.1 part order numbering figure 17 shows the part order numbering scheme for the 88sb2211. refer to marvell field application engineers (faes) or representatives for further information when ordering parts. figure 17: sample part number xx?lkj?c000?xxxx part number package code lkj = 128-pin lqfp environmental code 2 = green (rohs 6/6 and halogen-free) temperature code c = commercial i = industrial custom code custom code (optional) 88sb2211 custom code custom code table 28: 88sb2211 part order options package type part order number 128-pin lqfp 88SB2211XX-LKJ2C000 (commercial, green, rohs 6/6 and halogen-free package)
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 48 document classification: proprietary information february 27, 2008, preliminary 8.2 package marking figure is an example of the package marking and pin 1 location for the 88sb2211 lqfp package. lqfp package marking and pin 1 location 88sb-lkje lot number yyww xx@ country of origin 88sb2211xx marvell logo date code, custom code, assembly plant code yyww = date code (yy = year, ww = workweek) country of origin (contained in the mold id or marked as the last line on the part number, package co de, environmental code xxxx = part number aaa = package code e = environmental code (2 = green) note: the above drawing is not drawn to sca le. location of markings is approximate. pin 1 part number and custom code
marvell. moving forward faster register set appendix 88sb2211 register set
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 50 document classification: proprietary information february 27, 2008, preliminary this page intentionally left blank
list of registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 51 list of registers a.3 forward bridge mode configur ation registers............................................................................ 57 table 31: device and vendor id register ......................................................................................... ..................... 58 offset: 0x00000 table 32: forward bridge command and status register............................................................................ ......... 59 offset: 0x00004 table 33: class code and revision id register ................................................................................... ................. 62 offset: 0x00008 table 34: forward bridge bist header type and cache line size register........................................................ 62 offset: 0x0000c table 35: forward bridge pci express secondary lat ency timer and subordinate secondary and primary bus numbers register 63 offset: 0x00018 table 36: forward bridge pci express secondary status i/o limit and i/o base register.................................. 63 offset: 0x0001c table 37: memory limit and memory base register ................................................................................. ............ 65 offset: 0x00020 table 38: prefetchable memory limit and prefetchable memory base register ................................................... 6 6 offset: 0x00024 table 39: prefetchable base upper 32 bits register .............................................................................. ............... 67 offset: 0x00028 table 40: prefetchable limit upper 32 bits register............................................................................. ................. 67 offset: 0x0002c table 41: i/o limit upper 16 bits register and i/o base upper 16 bits ........................................................... ..... 67 offset: 0x00030 table 42: capabilities pointer register ......................................................................................... ......................... 68 offset: 0x00034 table 43: forward bridge control interrupt pin and interrupt line register ...................................................... .... 68 offset: 0x0003c table 44: power management capability header register ........................................................................... ........ 71 offset: 0x00040 table 45: forward bridge power management control and status register......................................................... 72 offset: 0x00044 table 46: forward bridge pci express capability register........................................................................ ........... 73 offset: 0x00048 table 47: forward bridge pci express device capabilities register ............................................................... ..... 74 offset: 0x0004c table 48: forward bridge pci express device control status register............................................................. ... 75 offset: 0x00050 table 49: forward bridge pci express link control status register ............................................................... ..... 78 offset: 0x00058 table 50: forward bridge pci internal arbiter control register .................................................................. .......... 79 offset: 0x00070 table 51: gpio control register................................................................................................. ........................... 80 offset: 0x00074 table 52: forward bridge pci clock output control register ...................................................................... ......... 81 offset: 0x00078
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 52 document classification: proprietary information february 27, 2008, preliminary table 53: forward bridge prefetch and crs control register ...................................................................... ........ 82 offset: 0x00080 table 54: marvell diagnostic pci express phy indirect access register ........................................................... .. 85 offset: 0x000f4 table 55: marvell diagnostic indirect address register.......................................................................... ............... 85 offset: 0x000f8 table 56: marvell diagnostic indirect data register ............................................................................. ................. 86 offset: 0x000fc table 57: pci express advanced error report header regist er..................................................................... ...... 86 offset: 0x00100 table 58: pci express uncorrectable error status register....................................................................... ........... 86 offset: 0x00104 table 59: pci express uncorrectable error mask register ......................................................................... .......... 87 offset: 0x00108 table 60: pci express uncorrectable error severity register..................................................................... .......... 89 offset: 0x0010c table 61: pci express correctable error status register ......................................................................... ............ 90 offset: 0x00110 table 62: pci express correctable error mask register ........................................................................... ............ 90 offset: 0x00114 table 63: pci express advanced error capability and control register............................................................ ... 91 offset: 0x00118 table 64: pci express header log first dword register ........................................................................... ....... 92 offset: 0x0011c table 65: pci express header log second dword register .......................................................................... ... 92 offset: 0x00120 table 66: pci express header log third dword register ........................................................................... ...... 92 offset: 0x00124 table 67: pci express header log fourth dword register .......................................................................... ..... 92 offset: 0x00128 table 68: pci uncorrectable error status register............................................................................... ................. 92 offset: 0x0012c table 69: forward bridge pci uncorrectable error mask register.................................................................. ...... 94 offset: 0x00130 table 70: pci uncorrectable error severity register............................................................................. ................ 95 offset: 0x00134 table 71: pci error capability and control register............................................................................. ................. 96 offset: 0x00138 table 72: pci header log first dword register ................................................................................... ............. 96 offset: 0x0013c table 73: pci header log second dword register .................................................................................. ......... 97 offset: 0x00140 table 74: pci header log third dword register ................................................................................... ............ 97 offset: 0x00144 table 75: pci header log fourth dword register .................................................................................. ........... 97 offset: 0x00148 a.4 reverse bridge mode configur ation registers............................................................................ 98 table 77: device and vendor id register ......................................................................................... ..................... 99 offset: 0x00000 table 78: reverse bridge command and status register............................................................................ ....... 100 offset: 0x00004
list of registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 53 table 79: class code and revision id register ................................................................................... ............... 103 offset: 0x00008 table 80: reverse bridge bist header type and cache line size register ..................................................... 10 4 offset: 0x0000c table 81: reverse bridge pci express secondary laten cy timer and subordinate secondary and primary bus numbers register 104 offset: 0x00018 table 82: reverse bridge pci express secondary status i/o limit and i/o base register................................ 105 offset: 0x0001c table 83: memory limit and memory base register ................................................................................. .......... 106 offset: 0x00020 table 84: prefetchable memory limit and prefetchable memory base register ................................................. 107 offset: 0x00024 table 85: prefetchable base upper 32 bits register .............................................................................. ............. 108 offset: 0x00028 table 86: prefetchable limit upper 32 bits register............................................................................. ............... 108 offset: 0x0002c table 87: i/o limit upper 16 bits register and i/o base upper 16 bits ........................................................... ... 108 offset: 0x00030 table 88: capabilities pointer register ......................................................................................... ....................... 109 offset: 0x00034 table 89: reverse bridge control interrupt pin and interrupt line register ...................................................... .. 109 offset: 0x0003c table 90: power management capability header register ........................................................................... ...... 112 offset: 0x00040 table 91: reverse bridge power management control and status register ...................................................... 11 3 offset: 0x00044 table 92: reverse bridge pci express capability register........................................................................ ......... 114 offset: 0x00048 table 93: reverse bridge pci express device capabilities register............................................................... ... 115 offset: 0x0004c table 94: reverse bridge pci express device control status register............................................................. . 116 offset: 0x00050 table 95: reverse bridge pci express link control status register ............................................................... ... 118 offset: 0x00058 table 96: reverse bridge pci express slot capabilities register................................................................. ...... 119 offset: 0x0005c table 97: reverse bridge pci express slot control status register ............................................................... ... 121 offset: 0x00060 table 98: reverse bridge pci express root control capabilities register......................................................... 122 offset: 0x00064 table 99: reverse bridge pci express root status register....................................................................... ....... 123 offset: 0x00068 table 100: gpio control register................................................................................................ .......................... 124 offset: 0x00074 table 101: reverse bridge pci clock output control register ..................................................................... ........ 124 offset: 0x00078 table 102: reverse bridge prefetch and crs control register..................................................................... ....... 125 offset: 0x00080 table 103: marvell diagnostic pci express phy indirect access register .......................................................... . 129 offset: 0x000f4
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 54 document classification: proprietary information february 27, 2008, preliminary table 104: marvell diagnostic indirect address register......................................................................... .............. 129 offset: 0x000f8 table 105: marvell diagnostic indirect data register ............................................................................ ................ 129 offset: 0x000fc table 106: pci express advanced error report header regist er.................................................................... ..... 130 offset: 0x00100 table 107: pci express uncorrectable error status register...................................................................... .......... 130 offset: 0x00104 table 108: pci express uncorrectable error mask register ........................................................................ ......... 131 offset: 0x00108 table 109: pci express uncorrectable error severity register.................................................................... ......... 132 offset: 0x0010c table 110: pci express correctable error status register ........................................................................ ........... 133 offset: 0x00110 table 111: pci express correctable error mask register .......................................................................... ........... 134 offset: 0x00114 table 112: pci express advanced error capability and control register........................................................... .. 135 offset: 0x00118 table 113: pci express header log first dword register .......................................................................... ...... 135 offset: 0x0011c table 114: pci express header log second dword register ......................................................................... .. 135 offset: 0x00120 table 115: pci express header log third dword register .......................................................................... ..... 136 offset: 0x00124 table 116: pci express header log fourth dword register ......................................................................... .... 136 offset: 0x00128 table 117: pci uncorrectable error status register.............................................................................. ................ 136 offset: 0x0012c table 118: reverse bridge pci uncorrectable error mask register ................................................................. .... 137 offset: 0x00130 table 119: pci uncorrectable error severity register............................................................................ ............... 138 offset: 0x00134 table 120: pci error capability and control register............................................................................ ................ 139 offset: 0x00138 table 121: pci header log first dword register .................................................................................. ............ 140 offset: 0x0013c table 122: pci header log second dword register ................................................................................. ........ 140 offset: 0x00140 table 123: pci header log third dword register .................................................................................. ........... 141 offset: 0x00144 table 124: pci header log fourth dword register ................................................................................. .......... 141 offset: 0x00148
88sb2211 register set registers overview copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 55 a 88sb2211 register set a.1 registers overview ? section a.3, forward bridge mode co nfiguration registers, on page 57 ? section a.4, reverse bridge mode configuration registers, on page 98 a.2.1 register field type xxx codes the 88sb2211 registers are made up of up to 32-bit fields, where each field is associated with one or more bits. each of these register fields have a unique programming functionality and their operation is defined by the field?s type. the foll owing list describes the function of each type: table 29: standard register field type codes type description lh register field with latching high function. if status is high, then the register is set to one and remains set until a read operation is performed through the management interface or a reset occurs. ll register field with latching low function. if status is low, then the register is cleared to zero and remains cleared until a read operation is performed through the management interface or a reset occurs. retain the register value is retained after software reset is executed. ro read only. writing to this type of field may cause unpredictable results. roc read only clear. after read, register field is cleared to zero. rsvd reserved for future use. all reserved bits are read as zero unless otherwise noted. rw read and write. rw0c read-only status, write-0 to clear status register. register bits indicate status when read, a set bit indicates a status event may be cleared by writing a 0. writing a 1 to rw0c bits have no effect. rw1c read-only status, write-1 to clear status register. register bits indicate status when read, a set bit indicates a status event may be cleared by writing a 1. writing a 0 to rw1c bits have no effect. sc self-clear. writing a one to this register causes the desired function to be immediately executed, then the register field is cleared to zero when the function is complete.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 56 document classification: proprietary information february 27, 2008, preliminary special used in special cases where the register type functionality does not conform to any of the standard types listed in this table. refer to the description column of the register table for a full definition of the field/register type and functionality. update value written to the register field does not take effect until a software reset is executed. the value can still be read after it is written. wo write only. a write to the register field will tri gger an internal function and a read will return an undefined value. x these bits do not exist. table 29: standard register field type codes (continued) type description
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 57 a.3 forward bridge mode configuration registers the following table provides a summarized list of all of the forward bridge mode configuration registers, including the re gister names, their type, offset, and a reference to the corresponding table and page for a detailed description of each register and its fields. table 30: register map table for the forward bridge mode configuration registers register name offset table and page forward bridge mode configuration header device and vendor id register 0x00000 table 31, p. 58 forward bridge command and status register 0x00004 table 32, p. 59 class code and revision id register 0x00008 table 33, p. 62 forward bridge bist header type and cache line size register 0x0000c table 34, p. 62 forward bridge pci express secondary latency timer and subordinate secondary and primary bus numbers register 0x00018 table 35, p. 63 forward bridge pci express secondary status i/o limit and i/o base register 0x0001c table 36, p. 63 memory limit and memory base register 0x00020 table 37, p. 65 prefetchable memory limit and prefetchable memory base register 0x00024 table 38, p. 66 prefetchable base upper 32 bits register 0x00028 table 39, p. 67 prefetchable limit upper 32 bits register 0x0002c table 40, p. 67 i/o limit upper 16 bits register and i/o base upper 16 bits 0x00030 table 41, p. 67 capabilities pointer register 0x00034 table 42, p. 68 forward bridge control interrupt pin and interrupt line register 0x0003c table 43, p. 68 power management capability header register 0x00040 table 44, p. 71 forward bridge power management control and status register 0x00044 table 45, p. 72 forward bridge pci express capability register 0x00048 table 46, p. 73 forward bridge pci express device capabilities register 0x0004c table 47, p. 74 forward bridge pci express device control status register 0x00050 table 48, p. 75 forward bridge pci express link control status register 0x00058 table 49, p. 78 forward bridge mode device specific forward bridge pci internal arbiter control register 0x00070 table 50, p. 79 gpio control register 0x00074 table 51, p. 80 forward bridge pci clock output control register 0x00078 table 52, p. 81 forward bridge prefetch and crs control register 0x00080 table 53, p. 82 marvell diagnostic pci expr ess phy indirect access register 0x000f4 table 54, p. 85 marvell diagnostic indire ct address register 0x000f8 table 55, p. 85 marvell diagnostic indi rect data register 0x000fc table 56, p. 86
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 58 document classification: proprietary information february 27, 2008, preliminary a.3.1 forward bridge mo de configuration header forward bridge mode extended configuration space pci express advanced error report header register 0x00100 table 57, p. 86 pci express uncorrectabl e error status register 0x00104 table 58, p. 86 pci express uncorrectable error mask register 0x00108 table 59, p. 87 pci express uncorrectable error severity register 0x0010c table 60, p. 89 pci express correctable error status register 0x00110 table 61, p. 90 pci express correctable error mask register 0x00114 table 62, p. 90 pci express advanced error capability and control register 0x00118 table 63, p. 91 pci express header log first dword register 0x0011c table 64, p. 92 pci express header log second dword register 0x00120 table 65, p. 92 pci express header log third dword register 0x00124 table 66, p. 92 pci express header log fourth dword register 0x00128 table 67, p. 92 pci uncorrectable error status register 0x0012c table 68, p. 92 forward bridge pci uncorrectable error mask register 0x00130 table 69, p. 94 pci uncorrectable error severity register 0x00134 table 70, p. 95 pci error capability and control register 0x00138 table 71, p. 96 pci header log first dword register 0x0013c table 72, p. 96 pci header log second dword register 0x00140 table 73, p. 97 pci header log third dword register 0x00144 table 74, p. 97 pci header log fourth dword register 0x00148 table 75, p. 97 table 30: register map table for the forward bridge mode configuration registers (continued) register name offset table and page table 31: device and vendor id register offset: 0x00000 bit field type/initval description 15:0 venid ro 0x11ab vendor id this field identifies marvell as the vendor of the device. 31:16 devid ro 0x2211 device id
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 59 table 32: forward bridge command and status register offset: 0x00004 bit field type/initval description 0 ioen rw 0x0 i/o space enable. controls the 88sb2211response as a tar get to i/o transactions on the primary interface that address a device that resides behind the bridge. note: software should ensure that outs tanding transactions involving the bridge are completed prior to disabling this bit. 0 = disable: respond to all i/o requests on the primary interface with an unsupported request completion. forwar d all i/o transactions from the secondary interface to the primary interface. 1 = enable: forwarding of i/o requests to the secondary interface. 1 memen rw 0x0 memory space enable controls the 88sb2211 response as a target to memory accesses on the primary interface that addresses a device t hat resides behind the bridge in both the non-prefetchable and prefetchable memory ranges. note: software should ensure that outs tanding transactions involving the bridge are completed prior to disabling this bit. 0 = disable: respond to all memory requests on the primary interface as unsupported request received. forward all memory requests from the secondary interface to the primary interface. 1 = enable: forwarding of memory tr ansactions to the secondary interface. 2 masen rw 0x0 master enable controls the ability of the 88sb2211 to issue memory and i/o read/write requests on the primary interface. disabl ing this bit prevents the bridge from issuing any memory or i/o read/write requests on the primary interface. note: message signaled interrupt (msi)/enhanced message signaled interrupt (msi-x) transactions are in-band memory writes; disabling the bus master enable bit disables msi/msi-x transactions as well. when this bit is zero, the 88sb2211 di sables response as a target to all memory or i/o transactions on the secondary interface (they cannot be forwarded to the primary interface). this bit does not affect the issuing of completions on the primary interface or the forwarding of completions. note: software should ensure that outs tanding transactions involving the bridge are completed prior to disabling this bit. 0 = disable: do not initiate memory or i/o transactions on the primary interface and disable response to memory and i/o transactions on secondary interface. 1 = enable: the bridge to operate as a master on the primary interface for memory and i/o transactions forwar ded from the secondary interface. 3 reserved_3 ro 0x0 special cycle enable does not apply to pci express devices.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 60 document classification: proprietary information february 27, 2008, preliminary 4 reserved_4 rsvd 0x0 memory write and invalidate the 88sb2211 does not support forwarding of memory write requests from the pci express interface as memory write and invalidate transactions on the pci interface. 5 reserved_5 rsvd 0x0 vga palette snoop does not apply to pci express bridges. 6 perrres rw 0x0 parity error response this bit controls the 88sb2211?s setting of the status bit[24] in this register in response to a rece ived poisoned data error as a requester (master) on the pci express. note: the setting of this bit does not affect the detectedperr status bit. 0 = disabled: masdataperr assertion is disabled. 1 = enabled: masdataperr assertion is enabled. 7 reserved_7 rsvd 0x0 reserved 8 serren rw 0x0 pci_serrn enable this bit enables reporting of non-fatal and fatal errors to the root complex. upon detection of either non-fatal or fatal error by the 88sb2211, this bit controls the assertion of ssyserr stat us bit[30] in this register and the generation of a corresponding err_fatal or err_nonfatal error message. in addition, upon pci_serrn assertion detec ted on the pci interface, this bit controls the generation of a corresponding err_fatal or err_nonfatal error message. note: pci express uncorrectable error messages are reported if enabled either through this bit or through bits or in the pci express device control status. 0 = disable: reporting of non-fatal and fatal errors. 1 = enable: reporting of non-fatal and fatal errors. 9 prfbtben ro 0x0 primary fast back-to-back transactions enable does not apply to pci express devices. 0 = disable: generation of fast back- to-back transactions on the primary interface. 1 = enable: generation of fast back-to-back transactions on the primary interface. 10 reserved_10 ro 0x0 interrupt disable the 88sb2211 has no internal interrupt resources, and therefore, this bit has no effect. 0 = enabled: interrupt messages enabled. 1 = disabled: interrupt messages disabled. 18:11 reserved_18_11 rsvd 0x0 reserved table 32: forward bridge command and status register (continued) offset: 0x00004 bit field type/initval description
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 61 19 reserved_19 rsvd 0x0 interrupt status the 88sb2211 has no internal interrupt resources, and therefore, this bit has no effect. this bit is hardwired to 0. 0 = no_interrupt: asserted. 1 = interrupt: asserted. 20 caplist ro 0x1 capability list support this bit indicates that the 88sb2211 c onfiguration header includes capability list. 21 66mhzcap ro 0x0 primary 66 mhz capable does not apply to pci express devices. 22 reserved_22 rsvd 0x0 reserved 23 fbtbcap ro 0x0 primary fast back-to-back transactions capable does not apply to pci express devices. 24 masdataperr rw1c 0x0 master data parity error reports detection of uncorrectable data errors by the 88sb2211. this bit is set when bit[6] of th is register is set and either of the following occur: - the 88sb2211 receives a poisoned co mpletion on the pci express interface. - the 88sb2211 transmits a poisoned write request on the pci express interface. 26:25 devseltim ro 0x0 primary pci_devseln timing does not apply to pci express. 27 starabort rw1c 0x0 signaled target abort this bit is set when the 88sb2211 generates a completion with completer abort completion status in response to a request received on the pci express interface. 28 rtabort rw1c 0x0 received target abort this bit is set when the 88sb2211, as a requester (master), receives a completion with the status completer abort. 29 rmabort rw1c 0x0 received master abort this bit is set when the 88sb2211 re ceives a completion with unsupported request completion status on the pci express interface. table 32: forward bridge command and status register (continued) offset: 0x00004 bit field type/initval description
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 62 document classification: proprietary information february 27, 2008, preliminary 30 ssyserr rw1c 0x0 signaled system error this bit is set when the 88sb2211 sends an err_fatal or err_nonfatal message. this bit is not set if the field in this register is de-asserted. 31 detparerr rw1c 0x0 detected parity error this bit is set when the 88sb2211 receives a poisoned tlp on the pci express interface. note: the bit is set regardless of the state of the bit in this register. table 32: forward bridge command and status register (continued) offset: 0x00004 bit field type/initval description table 33: class code and revision id register offset: 0x00008 bit field type/initval description 7:0 revid ro 0x1 88sb2211 revision number 15:8 progif ro 0x0 register level programming interface 23:16 subclass ro 0x04 88sb2211 sub class -- pci-to-pci bridge 31:24 baseclass ro 0x06 88sb2211 base class -- bridge device table 34: forward bridge bist header type and cache line size register offset: 0x0000c bit field type/initval description 7:0 cacheline rw 0x00 88sb2211 cache line size this field specifies the system cac he line size in units of dwords. the value in this register is used by the 88sb2211 for the following purposes: 1. to determine the pci interface command type when forwarding memory read transactions from t he pci express interface. 2. to determine the read transactions pref etch size of the pci when acting as target. 8 = 32 bytes prefetch 16 = 64 bytes prefetch 32 = 128 bytes prefetch
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 63 15:8 reserved_15_8 rsvd 0x0 primary latency timer does not apply to pci express. those bits are hardwired to 0. 23:16 headtype ro 0x01 88sb2211 configuration header type type 1 single-function configuration header. 31:24 bist ro 0x00 built-in self test (bist) the 88sb2211 does not support bist. table 34: forward bridge bist header type and cache line size register (continued) offset: 0x0000c bit field type/initval description table 35: forward bridge pci express secondary latency timer and subordinate secondary and primary bus numbers register offset: 0x00018 bit field type/initval description 7:0 pribusnm rw 0x0 primary bus number note: this field is not captured from type 0 configuration write accesses. 15:8 secbusnm rw 0x0 secondary bus number used for type 1 configuration access handling. 23:16 subbusnm rw 0x0 subordinate bus number used for type 1 configuration access handling. 31:24 seclattimer rw 0x0 pci latency timer specifies (in pci clock units) the value of the latency timer value of the 88sb2211. used by pci master when acting as a requester. table 36: forward bridge pci express secondar y status i/o limit and i/o base register offset: 0x0001c bit field type/initval description 3:0 iobasetype ro 0x1 i/o base type indicates that the 88sb2211 supports 32-bit i/o addressing.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 64 document classification: proprietary information february 27, 2008, preliminary 7:4 iobase rw 0x0 i/o base defines the bottom address of the i/o address range that determines when to forward i/o transactions from one interface to the other. the upper 4 bits are writable and correspond to address bits [15:12]. the lower 12 bits are assumed to be 000h. the 16 bits corresponding to address bits [31:16] of the i/o address are defined in the i/o limit upper 16 bits register and i/o base upper 16 bits. 11:8 iolimittype ro 0x1 i/o limit type indicates that the 88sb2211 supports 32-bit i/o addressing. 15:12 iolimit rw 0x0 i/o limit defines the top address of the i/o address range that determines when to forward i/o transactions from one interface to the other. the upper 4 bits are writable and correspond to address bits [15:12]. the lower 12 bits are assumed to be fffh. the 16 bits corresponding to address bits [31:16] of the i/o address are defined in the i/o limit upper 16 bits register and i/o base upper 16 bits. note: if there are no i/o addresses on the secondary side of the bridge, this field can be programmed to a smaller value than the field. in that case, the bridge does not forward any i/o transactions from the primary interface to the secondary, and does forward all i/o transactions from the secondary interface to the primary interface. note: 20:16 reserved_20_16 rsvd 0x0 reserved 21 66mhzcap ro 0x1 66 mhz capable 22 reserved_22 rsvd 0x0 reserved 23 fbtbcap ro 0x1 fast back-to-back capable. indicates that the 88sb2211 bridge is abl e of responding to fast back-to-back transactions on the secondary bus. 24 datapar rw1c 0x0 master data parity error this bit is used to report the detection of an uncorrectable data error by the bridge. this bit is set if the bridge is the bus master of the transaction on the secondary interface, the bit in the forward bridge control interrupt pin and interrupt line register is set, and either of the following two conditions occur: - the bridge asserts pci_perrn on a read transaction. - the bridge detects pci_perrn asserted on a write transaction. if the bit is set to zero, this bit is not be set when an error is detected. 26:25 devseltim ro 0x1 pci_devseln timing indicates the 88sb2211 device?s pci_devseln timing as medium. table 36: forward bridge pci express secondary status i/o limit and i/o base register (continued) offset: 0x0001c bit field type/initval description
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 65 27 starabort rw1c 0x0 signaled target abort this bit reports the signaling of a target-a bort termination by the bridge when it responds as the target of a transaction on its secondary interface. 28 rtabort rw1c 0x0 received target abort this bit reports the detection of a target -abort termination by the bridge when it is the master of a transaction on its secondary interface. 29 rmabort rw1c 0x0 received master abort. this bit reports the detection of a mast er-abort termination by the bridge when it is the master of a transaction on its secondary interface. 30 rsyserr rw1c 0x0 received system error this bit reports the detection of an pci_serrn assertion on the secondary interface of the bridge. 31 detparerr rw1c 0x0 detected parity error this bit reports the detection of an uncor rectable address, attribute, or data error by the bridge on its secondary interf ace. this bit must be set when any of the following three conditions are true: - the bridge detects an uncorrectable addr ess or attribute error as a potential target. - the bridge detects an uncorrectable data e rror when it is the target of a write transaction. - the bridge detects an uncorrectable data error when it is the master of a read transaction (immediate read data). the bit is set irrespective of the state of the bit in the forward bridge control interrupt pin and interrupt line register. table 36: forward bridge pci express secondary status i/o limit and i/o base register (continued) offset: 0x0001c bit field type/initval description table 37: memory limit and memory base register offset: 0x00020 bit field type/initval description 3:0 reserved ro 0x0 this bit is hardwired to 0. 15:4 membase rw 0x0 memory base defines the bottom address of the memory address range that determines when to forward memory transactions from one interface to the other. these bits correspond to address bits [31:20] in the memory address. the lower 20 bits are assumed to be 00000h 19:16 reserved ro 0x00 this bit is hardwired to 0.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 66 document classification: proprietary information february 27, 2008, preliminary 31:20 memlimit rw 0x0 memory limit defines the top address of the memory address range that determines when to forward memory transactions from one interface to the other. these bits correspond to address bits [31:20] in the memory address. the lower 20 bits are assumed to be fffffh. note: if there are no memory-mapped i/o addresses on the secondary side of the bridge, the fiel d must be programmed to a smaller value than the field. if there is no prefetchable memory, and there is no memory-mapped i/o on the secondary side of the bridge, then the bridge does not forward any memory transactions from the primary bus to the secondary, and does forward all memory transactions from the secondary bus to the primary bus. note: table 37: memory limit and memory base register (continued) offset: 0x00020 bit field type/initval description table 38: prefetchable memory limit and prefetchable memory base register offset: 0x00024 bit field type/initval description 3:0 perbasetype ro 0x1 prefetchable memory base type indicates that the 88sb2211 supports 64-bit prefetchable memory addressing. 15:4 prebase rw 0x0 prefetchable memory base defines the bottom address of the prefetchable memory address range that determines when to forward memory transactions from one interface to the other. these bits correspond to address bits [31:20] in the memory address. the lower 20 bits are assumed to be 00000h. the prefetchable base address upper 32-bit register specifies the bit [63: 32] of the 64-bit prefetchable memory address. 19:16 prelimittype ro 0x1 prefetchable memory limit defines the top address of the prefetchable memory address range that determines when to forward memory transactions from one interface to the other. these bits correspond to address bits [31:20] in the memory address. the lower 20 bits are assumed to be fffffh. the prefetchable-limit upper 32-bit register specifies the bit [63:32] of the 64-bit prefetchable memory address. note: if there is no prefetchable memory, and there is no memory-mapped i/o on the secondary side of the bridge, then the bridge does not forward any memory transactions from the primary bus to the secondary, and does forward all memory transactions from the secondary bus to the primary bus. note:
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 67 31:20 prelimit rw 0x0 prefetchable memory limit defines the top address of the memory address range that determines when to forward memory transactions from one interface to the other. these bits correspond to address bits [31:20] in the memory address. the lower 20 bits are assumed to be fffffh. note: if there is no prefetchable memory, and there is no memory-mapped i/o on the secondary side of the bridge, then the bridge does not forward any memory transactions from the primary bus to the secondary, and does forward all memory transactions from the secondary bus to the primary bus. note: table 38: prefetchable memory li mit and prefetchable memory base register (continued) offset: 0x00024 bit field type/initval description table 39: prefetchable base upper 32 bits register offset: 0x00028 bit field type/initval description 31:0 prebaseup rw 0x0 prefetchable memory-base upper 32 bits defines the upper 32 bits of the bottom address of the prefetchable memory address range that determines when to fo rward memory transactions from one interface to the other. table 40: prefetchable limit upper 32 bits register offset: 0x0002c bit field type/initval description 31:0 prelimitup rw 0x0 prefetchable memory-limit upper 32 bits. defines the upper-limit of the 64-bit prefetchable memory address range that determines when to forward memory transactions from one interface to the other. table 41: i/o limit upper 16 bits register and i/o base upper 16 bits offset: 0x00030 bit field type/initval description 15:0 iobaseup rw 0x0 i/o base upper 16 bits defines the upper 16 bits of the bottom address of the i/o address range that determines when to forward i/o transactions from one interface to the other. 31:16 iolimitup rw 0x0 i/o limit upper 16 bits defines the upper-limit address of the 32-bit i/o memory address range that determines when to forward i/o transactions from one interface to the other.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 68 document classification: proprietary information february 27, 2008, preliminary table 42: capabilities pointer register offset: 0x00034 bit field type/initval description 7:0 capptr ro 0x40 capability list pointer the current value in this field points to the pci power management capability set in power management capability header at offset 0x40. 31:8 reserved rsvd 0x0 reserved table 43: forward bridge control interrupt pin and interrupt line register offset: 0x0003c bit field type/initval description 7:0 intline rw 0x0 provides interrupt line routing information. 15:8 intpin ro 0x0 indicates that the 88sb2211 does no t implement a virtual interrupt pin. 16 secperrresen rw 0x0 secondary parity error response enable controls the response of the bridge to uncorrectable address, attribute, and data errors on the secondary interface. if this bit is set, the bridge takes its normal action when an uncorrectable address, attribute, or data error is detected. if this bit is cleared, the br idge ignores any uncorrectable address, attribute, and data errors that it detects and continue normal operation. the bridge generates parity even if parity error reporting is disabled. also, the bridge forwards poisoned data from conv entional pci to pci express as an uncorrectable conventional pci data error, regardless of the setting of this bit. 0 = ignore: uncorrectable address, attribute, and data errors on the secondary interface. 1 = enable: uncorrectable address, attribute, and data error detection and reporting on the secondary interface. 17 secserren rw 0x0 secondary pci_serrn enable controls the forwarding of secondary interface pci_serrn assertions to the primary interface. the bridge transmits an err_fatal or err_nonfatal message, according to the severity leve l, on the primary interface when all of the following are true: - pci_serrn is asserted on the secondary interface. - this bit is set or advanced error reporting is supported and the pci_serrn assertion detected mask bit is clea r in the secondary uncorrectable error mask register. - the pci_serrn enable bit is set in the command register or the pci express-specific bits are set in the devi ce control register of the pci express capability structure. 0 = disable: the forwarding of pci_serrn from the secondary interface to err_fatal and err_nonfatal (pci_serrn might still be forwarded if the serr advanced error mask bit is cleared). 1 = enable: the forwarding of secondary pci_serrn to err_fatal or err_nonfatal.
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 69 18 isaen rw 0x0 isa enable controls the response of the bridge to isa i/o addresses. this applies only to i/o addresses that are enabled by the i/o base and i/o limit registers and are in the first 64 kb of pci i/o address space (0000 0000h to 0000 ffffh). if this bit is set, the bridge blocks any forwar ding from primary to secondary of i/o transactions addressing the last 768 byte s in each 1-kb block. in the opposite direction (secondary to primary), i/o tr ansactions are forwarded if they address the last 768 bytes in each 1-kb block. 0 = downstream: forward downstream all i/o addresses in the address range defined by the i/o base and i/o limit registers. 1 = upstream: forward upstream isa i/o addresses in the address range defined by the i/o base and i/o limit r egisters that are in the first 64 kb of the pci i/o address space (top 768 bytes of each 1-kb block). 19 vgaen rw 0x0 vga enable controls the response of the bridge to vg a-compatible addresses. if this bit is set, the bridge forwards the following ac cesses on the primary interface to the secondary interface (and, conversely , blocks the forwarding of these addresses from the secondary to the primary interface): - memory accesses in the range 000a 0000h to 000b ffffh - i/o addresses in the first 64 kb of t he i/o address space (address[31:16] for pci express are 0000h) and where address[9:0] is in the range of 3b0h to 3bbh or 3c0h to 3dfh (inclusive of isa address aliases). address[15:10] may possess any value and is not used in the decoding. if the vga enable bit is set, forwarding of vga addresses is independent of the value of the isa enable bit (located in the bridge control, interrupt pin and interrupt line), the i/o address range and memory address ranges defined by the i/o limit upper 16 bits register and i/o base upper 16 bits, the memory limit and memory base, and the prefet chable memory limit and prefetchable memory base of the bridge. the forwardi ng of vga addresses is qualified by the and bits in the command and status. 0 = donotforward: vga compatible memory and i/o addresses from the primary to the secondary interface (addresses defined above) unless they are enabled for forwarding by the defined i/o and memory address ranges. 1 = forward: vga compatible memory and i/o addresses (addresses defined above) from the primary interface to the secondary interface (if the and bits are set) independent of the i/o and memory address ranges and independent of the bit in this register. 20 vga16bitdec rw 0x0 vga 16-bit decode this bit enables the bridge to prov ide 16-bit decoding of vga i/o address precluding the decoding of alias addres ses every 1 kb. this bit only has meaning if the vga enable bit in this regist er is also set to 1, enabling vga i/o decoding and forwarding by the bridge. this read/write bit enables system configuration software to select between 10- and 16-bit i/o address decoding for all vga i/o register accesses that are forwarded from primary to secondary whenever the vga enable bit is set to 1. 0 = 10-bit_address: execute 10-bit add ress decodes on vga i/o accesses. 1 = 16-bit_address: execute 16-bit add ress decodes on vga i/o accesses. table 43: forward bridge control interrupt pin and interrupt line register (continued) offset: 0x0003c bit field type/initval description
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 70 document classification: proprietary information february 27, 2008, preliminary 21 mamode rw 0x0 master-abort mode controls the behavior of a bridge when it receives a master-abort termination (e.g., an unsupported request on pci express) on either interface. 0 = donotreport: master-aborts. when a ur response is received from pci express for non-posted transactions, return ffff ffffh on reads and complete i/o writes normally. when a master-abort is received on the secondary interface for posted transactions initiated from the primary interface, no action is taken (i.e., all data is discarded). 1 = report: ur completions from pci ex press by signaling target-abort on the secondary interface. for posted transa ctions initiated from the primary interface and master-aborted on the secondary interface, the bridge returns an err_nonfatal (by default) or err_fatal transaction (provided the bit is set in the command and status). the severity is selectable according to the advanced error reporting capability. 22 secbusrst rw 0x0 secondary bus reset forces the assertion of rst_outn on the secondary interface. the secondary rst_outn is asserted by the bridge when ever this bit is set. the primary bus interface and all configuration space regi sters are not affected by the setting of this bit. note: rst_outn is asserted for as long as this bit is set, and software must observe proper pci reset timing requirements. 0 = donotforce: assertion of rst_outn is not forced. 1 = force: assertion of rst_outn is forced. 23 scfbtben rsvd 0x0 pci fast back-to-back enable controls ability of the bridge to gener ate fast back-to-back transactions to different devices on the pci interface. 24 prdt rsvd 0x0 primary discard timer does not apply to pci express devices. 25 secdt rw 0x0 secondary discard timer controls the number of pci clock cycles that the bridge waits for a master on the secondary interface to repeat a de layed transaction request. the counter starts once the completion (pci expr ess completion associated with the delayed transaction request) has reached the head of the downstream queue of the bridge (i.e., all ordering requirements have been satisfied and the bridge is ready to complete the delayed transac tion with the originating master on the secondary bus). if the originating master does not repeat the transaction before the counter expires, the bridge deletes the delayed transaction from its queue and set the discard timer status bit. 0 = 2^15_pci: the secondary discard timer counts 2^15 pci clock cycles. 1 = 2^10_pci: the secondary discard timer counts 2^10 pci clock cycles. table 43: forward bridge control interrupt pin and interrupt line register (continued) offset: 0x0003c bit field type/initval description
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 71 26 dtstt rw1c 0x0 discard timer status this bit is set to a 1 when the secondary discard timer expires and a delayed completion is discarded from a queue in the bridge. 0 = no_discard: timer error 1 = discard: timer error 27 dtserren rw 0x0 discard timer pci_serrn enable this bit enables the bridge to generate ei ther an err_nonfatal (by default) or err_fatal transaction on the pci express interface when the secondary discard timer expires and a delayed tr ansaction is discarded from a queue in the bridge. the severity is selectable according to the advanced error reporting capability. 0 = donotgenerate: err_nonfatal or err_fatal on the primary interface as a result of the expiration of the secondary discard timer. note that an error message can still be sent if the delayed transaction discard timer expired mask bit in the advanced error reporting capability is clear. 1 = generate: err_nonfatal or err_fatal on the primary interface if the secondary discard timer expires and a delayed transaction is discarded from a queue in the bridge. 31:28 reserved rsvd 0x0 reserved table 43: forward bridge control interrupt pin and interrupt line register (continued) offset: 0x0003c bit field type/initval description table 44: power management capability header register offset: 0x00040 bit field type/initval description 7:0 capid ro 0x01 capability id current value identifies the pci power management capability. 15:8 nextptr ro 0x48 next item pointer current value points to pci express capability. 18:16 pmcver ro 0x2 pci power management capability version 20:19 reserved ro 0x0 pme clock does not apply to pci express. this field is hardwired to 0. 21 dsi ro 0x0 device specific initialization the 88sb2211 does not requires device specific initialization. 24:22 auxcur ro 0x1 auxiliary current requirements the 88sb2211 does not require current from vaux in d3cold state.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 72 document classification: proprietary information february 27, 2008, preliminary 25 d1sup ro 0x1 d1 support the 88sb2211 supports d1 power management state. 26 d2sup ro 0x1 d2 support the 88sb2211 supports d2 power management state. 31:27 pmesup ro 0x1f power management event (pme) support the 88sb2211 supports pme generation from d0, d1, d2, d3cold power management states. table 44: power management capability header register (continued) offset: 0x00040 bit field type/initval description table 45: forward bridge power management control and status register offset: 0x00044 bit field type/initval description 1:0 pmstate rw 0x0 power state this field controls the power management state of the 88sb2211. the device supports all power management states. note: a transition from state d3 to state d0 causes an internal reset to occur. in states d1, d2 and d3hot, pci expr ess memory and i/o accesses are disabled, as well as the interrupt emulation messages, and only configuration cycles are allowed. 0 = d0 1 = d1 2 = d2 3 = d3 7:2 reserved_7_2 rsvd 0x0 reserved 8 pme_en rw 0x0 pme enable controls pm_pme message generation. note: power on sticky bit--not initialize d by either fundamental or hot reset. 0 = disabled 1 = enabled 12:9 pmdatasel ro 0x0 data select data register is not implemented. 14:13 pmdatascale ro 0x0 data scale data register is not implemented.
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 73 15 pme_stat rw1c 0x0 in forward mode the 88sb2211 does not generate power management events (pme). this field is hardwired to 0. note: pme events are forwarded from the pci port to the pci express port, but this is not reflected in this fi eld as those events are not generated by the 88sb2211. 21:16 reserved_21_16 rsvd 0x0 reserved 22 b2b3sup ro 0x1 b2_b3 support for d3hot when set, indicates that, when the bridge is programmed to d3hot, its secondary bus pci clock is stopped and driven to 0 (b2). when cleared, indicates that, when the bridge is programmed to d3hot, its secondary bus has its power remov ed and its pci clocks stopped (b3). this bit is only meaningful if the bit is set. note: the 88sb2211 does not control the power of the pci bus, and, therefore, is reporting b2 suppo rt. if the system supports pci power removal upon d3, this field should be set to 0x0 via the twsi serial initialization process. (this bit can be written from the twsi port). 23 bpccen ro 0x1 bus power/clock control enable when set, indicates that the bus power/c lock control mechanism, as defined in section 4.7.1 of the pci power m anagement specification 1.1, is enabled. the bstate and the secondary clocks are controlled accordingly. note: to disable the bus power clock cont rol, this field should be set to 0x0 via the twsi serial initialization process. (this bit can be written from the twsi port). note: shutting down the pci express clock out for power management events by default is not enabled. 31:24 pmdata ro 0x0 power management data data register is not implemented. table 45: forward bridge power management control and status register (continued) offset: 0x00044 bit field type/initval description table 46: forward bridge pci express capability register offset: 0x00048 bit field type/initval description 7:0 capid ro 0x10 capability id the current value of this field identifies the pci express capability. 15:8 nextptr ro 0x0 next item pointer the current value of this field points to the end of the capability list (null).
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 74 document classification: proprietary information february 27, 2008, preliminary 19:16 capver ro 0x1 capability version this field indicates the pci express base spec 1.0a version of the pci-express capability. 23:20 devtype ro 0x7 device/port type pci express to pci/pci-x bridge 24 slotimp ro 0x0 slot implemented 29:25 intmsgnum ro 0x0 interrupt message number 31:30 reserved rsvd 0x0 reserved table 46: forward bridge pci express capability register (continued) offset: 0x00048 bit field type/initval description table 47: forward bridge pci express device capabilities register offset: 0x0004c bit field type/initval description 2:0 maxpldsizesup ro 0x0 maximum payload size supported 128b mps support. this bit is hardwired to 0. 4:3 phntmfncsup ro 0x0 phantom functions support phantom functions are not supported. this bit is hardwired to 0. 5 exttagsup ro 0x0 extended tag field support extended tag is not supported. this bit is hardwired to 0. 11:6 reserved_11_6 rsvd 0x0 reserved 12 attbutprs ro 0x0 attention button present the 88sb2211 does not support attention button. this bit is hardwired to 0. 13 attindprs ro 0x0 attention indicator present the 88sb2211 does not support attention indicator this bit is hardwired to 0.
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 75 14 pwrindprs ro 0x0 power indicator present the 88sb2211 does not support attention indicator. this bit is hardwired to 0. 15 role-based error reporting ro 0x0 the 88sb2211 does not support role based error reporting. 17:16 reserved_17_16 rsvd 0x0 reserved 25:18 capsplval ro 0x0 captured slot power limit value 27:26 capsplscl ro 0x0 captured slot power limit scale 31:28 reserved_31_28 rsvd 0x0 reserved table 47: forward bridge pci express devi ce capabilities register (continued) offset: 0x0004c bit field type/initval description table 48: forward bridge pci express device control status register offset: 0x00050 bit field type/initval description 0 corerrrepen rw 0x0 correctable error reporting enable controls error message generation on behalf of errors on both the pci express and conventional pci interfaces. 0 = masked: err_cor error messages ar e masked. status bit is not masked. 1 = enabled: err_cor error messages enabled. 1 nferrrepen rw 0x0 non-fatal error reporting enable controls error message generation on behalf of errors on both the pci express and conventional pci interfaces. note: err_nonfatal error messages are still enabled when this field is 0, if the bit in the command and status is set. 0 = masked: err_nonfatal error mess ages are masked. status bit is not masked. 1 = enabled: err_nonfatal error messages enabled. 2 ferrrepen rw 0x0 fatal error reporting enable controls error message generation on behalf of errors on both the pci express and conventional pci interfaces. note: err_fatal error messages are still enabled when this field is 0, if the bit in the command and status is set. 0 = masked: err_fatal error messages are masked. status bit is still affected. 1 = enabled: err_fatal error messages enabled.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 76 document classification: proprietary information february 27, 2008, preliminary 3 urrepen rw 0x0 unsupported request (ur) reporting enable controls error reporting on behalf of unsupported request errors detected on the pci express interface only. note: ur related error messages are still enabled when urrepen=0, if the bit in the command and status is set. 0 = masked: ur related error messages are masked. status bit is not masked. 1 = enabled: ur related error messages enabled. 4 enro ro 0x0 enable relaxed ordering the 88sb2211 never sets the relaxed ordering attribute in transactions it initiates as a requester. this bit is hardwired to 0. 7:5 maxpldsz rw 0x0 maximum payload size the maximum payload size supported is 128b (refer to bit in the pci express device capabilities). 0 = 128b 1-7 reserved 8 reserved_8 ro 0x0 extended tag field enabled not supported. this bit is hardwired to 0. 9 reserved_9 ro 0x0 phantom function enable not supported. this bit is hardwired to 0. 10 auxpwren rw 0x0 auxiliary (aux) power pm enable controls allocation of aux power to the device. note: power on reset sticky bit is not initialized by either fundamental or hot reset. 0 = disabled: vaux is not allocated. 1 = enabled: vaux is allocated. 11 enns ro 0x0 enable no snoop the 88sb2211 never sets the no snoop attribute in transactions it initiates as a requester. this bit is hardwired to 0. 14:12 maxrdrqsz rw 0x2 maximum read request size this field limits the 88sb2211 maxi mum read request size as a requestor (master). 0 = 128b 1 = 256b 2 = 512b 3 = 1_kb 4 = 2_kb 5 = 4_kb table 48: forward bridge pci express device control status register (continued) offset: 0x00050 bit field type/initval description
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 77 15 brcrsen rw 0x0 bridge configuration retry enable when set, this bit enables the 88sb2211 to return configuration request retry status (crs) in response to a configuration request that targets a device below the bridge. 16 corerrdet rw1c 0x0 correctable error detected this bit indicates the status of t he correctable errors detected by the 88sb2211. it set for the corresponding errors on both the pci express and conventional pci interfaces. 17 nferrdet rw1c 0x0 non-fatal error detected this bit indicates the status of the non-fatal errors detected by the 88sb2211. it is set for the corresponding errors on both the pci express and conventional pci interfaces. 18 ferrdet rw1c 0x0 fatal error detected this bit indicates the status of the fatal errors detected by the 88sb2211. it is set for the corresponding errors on both the pci express and conventional pci interfaces. 19 urdet rw1c 0x0 unsupported request detected this bit indicates that the 88sb 2211 receives an unsupported request. it is set for the corresponding errors on both the pci express and conventional pci interfaces. 20 auxpwrdet ro 0x0 aux power detected indicates that the 88sb2211 detected aux power. 21 transpend ro 0x0 transactions pending the 88sb2211 does not issue non-posted requests on its own behalf. this bit is hardwired to 0. 31:22 reserved_31_22 rsvd 0x0 reserved table 48: forward bridge pci express device control status register (continued) offset: 0x00050 bit field type/initval description
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 78 document classification: proprietary information february 27, 2008, preliminary table 49: forward bridge pci express link control status register offset: 0x00058 bit field type/initval description 1:0 aspm_cnt rw 0x0 active state link pm control this field controls the level of ac tive state pm supported on the link. 0 = disabled 1 = l0s_entry_supported 2 = reserved 3 = l0s_l1_entry_supported 2 reserved_2 rsvd 0x0 reserved 3 rcb ro 0x0 read completion boundary not applicable to the 88sb2211. this bit is hardwired to 0. 4 reserved_4 ro 0x0 reserved 5 reserved_5 ro 0x0 reserved 6 cmnclkcfg rw 0x0 common clock configuration when set by software, this bit indicate s that both devices on the link use a distributed common reference clock. 7 extdsnc rw 0x0 extended sync when set, this bit forces extended transmission of 4096 fts ordered sets followed by a single skip ordered set in exit from l0s and extra (1024) ts1 at exit from l1. note: this bit is used for test and measurement only. note: 15:8 reserved_15_8 rsvd 0x0 reserved 19:16 lnkspd ro 0x1 link speed the only link speed available is 2.5 gbps. 0 = reserved 1 = 2.5 gbps 2-15 = reserved the value of this field is un defined when the link is not up. 25:20 neglnkwdth ro 0x0 negotiated link width the only link width available is x1. 0 = reserved 1 = x1 2-63 = reserved the value of this field is un defined when the link is not up. 26 reserved_26 ro 0x0 reserved
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 79 a.3.2 forward bridge mode device specific 27 lnktrn ro 0x0 link training this bit indicates that link training is in progress. this bit is cleared once li nk training is complete. 28 sltclkcfg ro 0x1 slot clock configuration . 0 = independentclock: the 88sb2211 uses an independent clock, irrespective of the presence of a refer ence clock on the connector. 1 = referenceclock: the 88sb2211 uses the reference clock that the platform provides. 31:29 reserved_31_29 rsvd 0x0 reserved table 49: forward bridge pci express link control status register (continued) offset: 0x00058 bit field type/initval description table 50: forward bridge pci inte rnal arbiter control register offset: 0x00070 bit field type/initval description 0 internalarben ro sar enable internal arbiter operation note: initial value is strapped on reset, from pci_gnt1n signal. 0 = disable 1 = enable 1 brokendeten rw 0x0 broken master detection enable if set to 1, broken master detection is enabled. a master is said to be broken if it fails to respond to grant assert ion within a timeout specified in field. 0 = disabled: broken master detection disabled 1 = enabled: broken master detection enabled 5:2 brokenvalue rw 0xf broken master detection value the value sets the maximum number of pci clock cycles that the arbiter waits for a pci master to respond to its grant assertion. if a pci master fails to assert pci_framen within this time, the pci arbiter aborts the transaction and performs a new arbitration cycle. 0-3 = reserved. do not use. 4 = allows 2 pci clock cycles for a broken master detection. 5 = allows 3 pci clock cycles for a broken master detection. ... 16 = allows 13 pci cloc k cycles for a broken master detection. note: the set value must be greater than 3.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 80 document classification: proprietary information february 27, 2008, preliminary 6 brokendet rw1c 0x0 broken master detected reports if a broken master was detected. this bit is set upon broken master detection. it remains asserted until cleared by writing 1. 0 = detected: broken master was detected. 1 = not detected: broken master was not detected. 7 reserved_7 rsvd 0x0 reserved 14:8 parkingdis rw 0x0 parking disable note: the arbiter parks on the last master granted unless disabled through the parkingdis bit. when parkingdis is all 1s, the pci arbiter parks on the internal pci master. parkingdis[0] corresponds to the internal pci master. parkingdis[x] corresponds to external agent x (reqn or gntn signals). 0 = enabled: parking on the a ssociated pci master is enabled. 1 = disabled: parking on the associated pci master is disabled. 15 reserved_15 rw 0x1 reserved 16 reserved_16 rw 0x1 reserved 31:17 reserved_31_17 rsvd 0x0 reserved table 50: forward bridge pci internal ar biter control register (continued) offset: 0x00070 bit field type/initval description table 51: gpio control register offset: 0x00074 bit field type/initval description 7:0 gpioouten rw 0x0 general purpose i/o output enable controls the direction of the gpio si gnal. by default all gpio pins are inputs. note: gpioouten[n] controls gpio[n] pin, n=0..7 0 = input 1 = output 15:8 gpiodataout rw 0x0 general purpose i/o data out controls the data driven on the gpio pins, when configured as an output by the field. note: gpiodataout[n] controls gpio[n] pin, n=0..7 23:16 gpiodatain ro 0x0 general purpose i/o data in reads the current state of the gpio pin. valid only when gpio pin is configured as an input by the field. note: gpiodatain[n] reads gpio[n] pin, n=0..7
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 81 31:24 reserved rsvd 0x0 reserved table 51: gpio control register (continued) offset: 0x00074 bit field type/initval description table 52: forward bridge pci clock output control register offset: 0x00078 bit field type/initval description 0 clockoutdis0 rw sar pci clock out 0 disable controls the activation of pci_clk_ out[0]. when set, pci_clk_out[0] is driven to 0. the initial value of this field is sampled at reset from pci_reqn[0] pin. refer to the reset strapping in section "reset configuration". 0 = enabled: pci clock enabled 1 = disabled: pci clock disabled 1 clockoutdis1 rw sar pci clock out 1 disable controls the activation of pci_clk_ out[1]. when set, pci_clk_out[1] is driven to 0. the initial value of this field is sampled at reset from pci_reqn[1] pin. refer to the reset strapping in section "reset configuration". 0 = enabled: pci clock enabled 1 = disabled: pci clock disabled 2 clockoutdis2 rw sar pci clock out 2 disable controls the activation of pci_clk_ out[2]. when set, pci_clk_out[2] is driven to 0. the initial value of this field is sampled at reset from pci_reqn[2] pin. refer to reset strapping in section "reset configuration". 0 = enabled: pci clock enabled 1 = disabled: pci clock disabled 3 clockoutdis3 rw sar pci clock out 3 disable controls the activation of pci_clk_ out[3]. when set, pci_clk_out[3] is driven to 0. the initial value of this field is sampled at reset from pci_reqn[3] pin. refer to reset strapping in section "reset configuration". 0 = enabled: pci clock enabled 1 = disabled: pci clock disabled 4 clockoutdis4 rw sar pci clock out 4 disable controls the activation of pci_clk_ out[4]. when set, pci_clk_out[4] is driven to 0. the initial value of this field is sampled at reset from pci_reqn[4] pin. refer to reset strapping in section "reset configuration". 0 = enabled: pci clock enabled 1 = disabled: pci clock disabled
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 82 document classification: proprietary information february 27, 2008, preliminary 5 clockoutdis5 rw sar pci clock out 5 disable controls the activation of pci_clk_ou t[5] when set, pci_clk_out[5] is driven to 0. the initial value of this field is sampl ed at reset from pci_reqn[4:0] pins. if all are strapped low, pci_clk_out[5] is disabled. refer to reset strapping in section "reset configuration". 0 = enabled: pci clock enabled 1 = disabled: pci clock disabled 31:6 reserved rsvd 0x0 reserved table 52: forward bridge pci clock output control register (continued) offset: 0x00078 bit field type/initval description table 53: forward bridge prefetch and crs control register offset: 0x00080 bit field type/initval description 1:0 mrmprftchmd rw 0x3 read multiple prefetch mode 0 = prefetch_disabled 1 = prefetch_enabled 2 = reserved 3 = aggressive_prefetch_enabled 2 mrmaggrinitwm rw 0x1 memory read multiple aggressive prefetch initial read water mark controls the number of 128-bytes buffers to be pre-fetched initially. note: relevant only if aggressive prefetch is enabled by the bit. 0 = two: the 88sb2211 pre-fetches two 128-bytes buffers initially. 1 = three: the 88sb2211 pre-fetches three 128-bytes buffers initially. 5:3 mrmaggrnextwm rw 0x0 memory read multiple aggressive prefetch next read watermark controls the criteria for issuing the next prefetch read request on the pci express interface. note: relevant only if aggressive prefetch is enabled by the bit. 0 = one data cycle: fetch next buffer after one data cycle is driven on the bus. 1 = two data cycles: fetch next buffer after two data cycles are driven on the bus. 2 = three data cycles: fetch next buffer after three data cycles are driven on the bus. 3 = four data cycles: fetch next buffer after four data cycles are driven on the bus. 4 = five data cycles: fetch next buffer af ter five data cycles are driven on the bus. 5 = six data cycles: fetch next buffer af ter six data cycles are driven on the bus. 6 = seven data cycles: fetch next buffer after seven data cycles are driven on the bus. 7 = eight data cycles: fetch next buffer after eight data cycles are driven on the bus.
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 83 6 mrmaggrreswm rw 0x0 memory read multiple aggressive prefetch response watermark controls the criteria for responding to the delayed read on the pci bus. note: relevant only if aggressive prefetch is enabled by the bit. 0 = one: the 88sb2211 drives read dat a on the bus as soon as it has one 128-byte read buffer. 1 = two: the 88sb2211 drives read data on the bus as soon as it has two 128-byte read buffers. 7 reserved_7 ro 0x1 reserved 9:8 mrlprftchmd rw 0x1 memory read line prefetch mode 0 = prefetch_disabled 1 = prefetch_enabled 2 = reserved 3 = aggressive_prefetch_enabled 10 mrlaggrinitwm rw 0x0 memory read line aggressive prefetch initial read watermark controls the number of 128-bytes buffers to be pre-fetched initially. note: relevant only if aggressive prefetch is enabled by the bit. 0 = two: the 88sb2211 pre-fetches two 128-bytes buffers initially. 1 = three: the 88sb2211 pre-fetches three 128-bytes buffers initially. 13:11 mrlaggrnextwm rw 0x0 memory read line aggressive prefetch next read watermark controls the criteria for issuing the next prefetch read request on the pci express interface. note: relevant only if aggressive prefetch is enabled by the bit. 0 = one data cycle: fetch next buffer after one data cycle is driven on the bus. 1 = two data cycles: fetch next buffer after two data cycles are driven on the bus. 2 = three data cycles: fetch next buffer after three data cycles are driven on the bus. 3 = four data cycles: fetch next buffer after four data cycles are driven on the bus. 4 = five data cycles: fetch next buffer af ter five data cycles are driven on the bus. 5 = six data cycles: fetch next buffer af ter six data cycles are driven on the bus. 6 = seven data cycles: fetch next buffer after seven data cycles are driven on the bus. 7 = eight data cycles: fetch next buffer after eight data cycles are driven on the bus. table 53: forward bridge prefetch and crs control register (continued) offset: 0x00080 bit field type/initval description
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 84 document classification: proprietary information february 27, 2008, preliminary 14 mrlaggrreswm rw 0x0 memory read multiple aggressive prefetch response watermark controls the criteria for responding to the delayed read on the pci bus. note: relevant only if aggressive prefetch is enabled by the bit. 0 = one: the 88sb2211 drives read dat a on the bus as soon as it has one 128-byte read buffer. 1 = two: the 88sb2211 drives read data on the bus as soon as it has two 128-byte read buffers. 15 reserved_15 rw 0x0 reserved 17:16 mrprftchmd rw 0x0 memory read prefetch mode 0 = prefetch_disabled 1 = prefetch_enabled 2 = reserved 3 = aggressive_prefetch_enabled 18 mraggrinitwm rw 0x0 memory read aggressive prefetch initial read watermark controls the number of 128-bytes buffers to be pre-fetched initially. note: relevant only if aggressive prefetch is enabled by the bit. 0 = two: the 88sb2211 pre-fetches two 128-bytes buffers initially. 1 = three: the 88sb2211 pre-fetches three 128-bytes buffers initially. 21:19 mraggrnextwm rw 0x0 memory read aggressive prefetch next read watermark controls the criteria for issuing the next prefetch read request on the pci express interface. note: relevant only if aggressive prefetch is enabled by the bit. 0 = one data cycle: fetch next buffer after one data cycle is driven on the bus. 1 = two data cycles: fetch next buffer after two data cycles are driven on the bus. 2 = three data cycles: fetch next buffer after three data cycles are driven on the bus. 3 = four data cycles: fetch next buffer after four data cycles are driven on the bus. 4 = five data cycles: fetch next buffer af ter five data cycles are driven on the bus. 5 = six data cycles: fetch next buffer af ter six data cycles are driven on the bus. 6 = seven data cycles: fetch next buffer after seven data cycles are driven on the bus. 7 = eight data cycles: fetch next buffer after eight data cycles are driven on the bus. table 53: forward bridge prefetch and crs control register (continued) offset: 0x00080 bit field type/initval description
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 85 22 mraggrreswm rw 0x0 memory read aggressive prefetch response watermark controls the criteria for responding to the delayed read on the pci bus. note: relevant only if aggressive prefetch is enabled by the bit. 0 = one: the 88sb2211 drives read dat a on the bus as soon as it has one 128-byte read buffer. 1 = two: the 88sb2211 drives read data on the bus as soon as it has two 128-byte read buffers. 23 reserved_23 rw 0x0 reserved 24 reserved_24 rw 0x1 reserved always write 1. 25 reserved_25 rw 0x1 reserved always write 1. 26 reserved_26 rw 0x0 reserved always write 0. 27 reserved_27 rw 0x0 reserved always write 0. 28 reserved_28 rw 0x0 reserved 29 reserved_29 rw 0x0 reserved 31:30 reserved_31_30 rw 0x0 reserved table 53: forward bridge prefetch and crs control register (continued) offset: 0x00080 bit field type/initval description table 54: marvell diagnostic pci express phy indirect access register offset: 0x000f4 bit field type/initval description 31:0 reserved rsvd 0x84cce5 reserved table 55: marvell diagnostic indirect address register offset: 0x000f8 bit field type/initval description 1:0 reserved rsvd 0x0 reserved
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 86 document classification: proprietary information february 27, 2008, preliminary a.3.3 forward bridge mode e xtended configuration space 13:2 address rw 0x0 reserved note: for marvell usage only. 31:14 reserved_31_14 rsvd 0x0 reserved table 55: marvell diagnostic indirect address register (continued) offset: 0x000f8 bit field type/initval description table 56: marvell diagnostic indirect data register offset: 0x000fc bit field type/initval description 31:0 data ro 0x0 reserved note: for marvell usage only. table 57: pci express advanced error report header register offset: 0x00100 bit field type/initval description 15:0 pecapid ro 0x1 extended capability id the current value of this field id entifies the advanced error reporting capability. 19:16 capver ro 0x1 capability version 31:20 nextptr ro 0x0 next item pointer this field indicates the last item in the extended capabilities linked list. table 58: pci express uncorrectable error status register offset: 0x00104 bit field type/initval description 3:0 reserved rsvd 0x0 reserved 4 dlprterr rw1c 0x0 data link protocol error status
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 87 11:5 reserved rsvd 0x0 reserved 12 rpsntlperr rw1c 0x0 poisoned tlp status 13 fcprterr rw1c 0x0 flow control protocol error status set upon dllp update timeout (200s with no fc dllp received). 14 cmptoerr rw1c 0x0 completion timeout status 15 caerr rw1c 0x0 completer abort status 16 unexpcmperr rw1c 0x0 unexpected completion status 17 reserved rsvd 0x0 reserved 18 malftlperr rw1c 0x0 malformed tlp status 19 reserved rsvd 0x0 reserved 20 urerr rw1c 0x0 unsupported request error status 31:21 reserved rsvd 0x0 reserved table 58: pci express uncorrectable error status register (continued) offset: 0x00104 bit field type/initval description table 59: pci express uncorrectable error mask register offset: 0x00108 bit field type/initval description 3:0 reserved rsvd 0x0 reserved
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 88 document classification: proprietary information february 27, 2008, preliminary 4 dlprterrmsk rw 0x0 data link protocol error mask when an error is indicated in the pci express uncorrectable error status and the corresponding bit is set: - the header is not logged in the header log register - the first error pointer is not updated - an error message is not generated. the status bit is set regardless of the mask setting. 0 = not_masked 1 = masked 11:5 reserved rsvd 0x0 reserved 12 rpsntlperrmsk rw 0x0 poisoned tlp error mask 13 fcprterrmsk rw 0x0 flow control protocol error mask 14 cmptoerrmsk rw 0x0 completion timeout mask 15 caerrmsk rw 0x0 completer abort mask 16 unexpcmperrmsk rw 0x0 unexpected completion mask 17 reserved rsvd 0x0 reserved 18 malftlperrmsk rw 0x0 malformed tlp mask 19 reserved rsvd 0x0 reserved 20 urerrmsk rw 0x0 unsupported request error mask 31:21 reserved rsvd 0x0 reserved table 59: pci express uncorrectable error mask register (continued) offset: 0x00108 bit field type/initval description
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 89 table 60: pci express uncorrectable error severity register offset: 0x0010c bit field type/initval description 3:0 reserved rsvd 0x1 reserved 4 dlprterrsev rw 0x1 data link protocol error severity controls the severity indication of the uncorrectable errors. each bit controls the error type of the corresponding bit in the pci express uncorrectable error status. 0 = non-fatal: error type is non-fatal. 1 = fatal: error type is fatal. 11:5 reserved rsvd 0x0 reserved 12 rpsntlperrsev rw 0x0 poisoned tlp error severity 13 fcprterrsev rw 0x1 flow control protocol error severity 14 cmptoerrsev rw 0x0 completion timeout severity 15 caersev rw 0x0 completer abort severity 16 unexpcmperrsev rw 0x0 unexpected completion severity 17 reserved rsvd 0x0 reserved 18 malftlperrsev rw 0x1 malformed tlp severity 19 reserved rsvd 0x0 reserved 20 urerrsev rw 0x0 unsupported request error severity 31:21 reserved rsvd 0x0 reserved
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 90 document classification: proprietary information february 27, 2008, preliminary table 61: pci express correctable error status register offset: 0x00110 bit field type/initval description 0 rcverr rw1c 0x0 receiver error status when set, this bit indicates that a receiver error has occurred. 5:1 reserved rsvd 0x0 reserved 6 badtlperr rw1c 0x0 bad tlp status 7 baddllperr rw1c 0x0 bad dllp status 8 rplyrllovrerr rw1c 0x0 replay number rollover status 11:9 reserved rsvd 0x0 reserved 12 rplytoerr rw1c 0x0 replay timer timeout status 31:13 reserved rsvd 0x0 reserved table 62: pci express correctable error mask register offset: 0x00114 bit field type/initval description 0 rcvmsk rw 0x0 receiver error mask if set, an error message is not generated upon occurrence of a receiver error. 0 = not_masked 1 = masked 5:1 reserved_5_1 rsvd 0x0 reserved 6 badtlpmsk rw 0x0 bad tlp mask 7 baddllperrmsk rw 0x0 bad dllp mask 8 rplyrllovrmsk rw 0x0 replay number rollover mask
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 91 11:9 reserved_11_9 rsvd 0x0 reserved 12 rplytomsk rw 0x0 replay timer timeout mask 13 advisorynonfatalerr or ro 0x0 advisory non-fatal error 31:14 reserved_31_14 rsvd 0x0 reserved table 62: pci express correctable error mask register (continued) offset: 0x00114 bit field type/initval description table 63: pci express advanced error capability and control register offset: 0x00118 bit field type/initval description 4:0 frsterrptr ro 0x0 first error pointer this field reports the bit position of t he first error reported in the pci express uncorrectable error status. this field locks upon receipt of the first uncorrectable error that is not masked. it remains locked until software clears it by writing 1 to the corresponding status bit. upon receipt of the next uncorrectable error that is not masked, the field locks again until cleared as described above. this lock and clear process continues to repeat itself. 4 = frsterrptr_4: data link protocol error 12 = frsterrptr_12: poisoned tlp error 13 = frsterrptr_13: flow control protocol error 14 = frsterrptr_14: completion timeout error 15 = frsterrptr_15: completer abort status 16 = frsterrptr_16: unexpected completion error 18 = frsterrptr_18: malformed tlp error 20 = frsterrptr_20: unsupported request error 31:5 reserved rsvd 0x0 reserved
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 92 document classification: proprietary information february 27, 2008, preliminary table 64: pci express header log first dword register offset: 0x0011c bit field type/initval description 31:0 hdrlog1dw ro 0x0 header log first dword logs the header of the first error reported in the pci express uncorrectable error status. this field locks upon receipt of the first uncorrectable error that is not masked. it remains locked until the software clears it by writing 1 to the corresponding status bit. upon receipt of the next uncorrectable error that is not masked, the field locks again until clear ed as described above. this lock and clear process continues to repeat itself. table 65: pci express header log second dword register offset: 0x00120 bit field type/initval description 31:0 hdrlog2dw ro 0x0 header log second dword table 66: pci express header log third dword register offset: 0x00124 bit field type/initval description 31:0 hdrlog3dw ro 0x0 header log third dword table 67: pci express header log fourth dword register offset: 0x00128 bit field type/initval description 31:0 hdrlog4dw ro 0x0 header log fourth dword table 68: pci uncorrectable error status register offset: 0x0012c bit field type/initval description 0 reserved_0 rsvd 0x0 target-abort on split completion status does not apply to conventional pci.
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 93 1 reserved_1 rsvd 0x0 master-abort on split completion status does not apply to conventional pci. 2 rcvta rw1c 0x0 received target-abort status 3 rcvma rw1c 0x0 received master-abort status 6:4 reserved_6_4 rsvd 0x0 reserved 7 ucdataerr rw1c 0x0 uncorrectable data error status 8 reserved_8 rsvd 0x0 uncorrectable attribute error status does not apply to conventional pci. 9 ucaddrerr rw1c 0x0 uncorrectable address error status 10 dtexp rw1c 0x0 delayed transaction discard timer expired status no header log. 11 perrdetected rw1c 0x0 pci_perrn assertion detected 12 serrdetected rw1c 0x0 pci_serrn assertion detected no header log. 13 internalbrerr rw1c 0x0 internal bridge error status no header log. 31:14 reserved_31_14 rsvd 0x0 reserved table 68: pci uncorrectable error status register (continued) offset: 0x0012c bit field type/initval description
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 94 document classification: proprietary information february 27, 2008, preliminary table 69: forward bridge pci uncorrectable error mask register offset: 0x00130 bit field type/initval description 0 reserved_1_0 rsvd 0x0 reserved 1 reserved_1 rw 0x0 reserved 2 rcvtamsk rw 0x0 received target-abort mask status bit is set regardless of the mask setting. 0 = not_masked 1 = masked 3 rcvmamsk rw 0x1 received master-abort mask 4 reserved_4 rsvd 0x0 reserved 6:5 reserved_6_5 rw 0x1 reserved 7 ucdataerrmsk rw 0x1 uncorrectable data error mask 8 ucattrerrmsk rw 0x1 uncorrectable attribute error mask 9 ucaddrerrmsk rw 0x1 uncorrectable address error mask sar upon ep/rc mode. 10 dtexp rw 0x1 delayed transaction discard timer expired mask header in not logged. sar upon ep/rc mode. 11 perrdetectedmsk rw 0x0 pci_perrn assertion detected mask 12 serrdetectedmsk rw 0x1 pci_serrn assertion detected mask header in not logged. 13 internalbrerrmsk rw 0x0 internal bridge error mask no header log.
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 95 31:14 reserved_31_14 rsvd 0x0 reserved table 69: forward bridge pci uncorrectable error mask register (continued) offset: 0x00130 bit field type/initval description table 70: pci uncorrectable error severity register offset: 0x00134 bit field type/initval description 0 reserved_1_0 rsvd 0x0 reserved 1 reserved_1 rw 0x0 reserved 2 rcvtasev rw 0x0 received target-abort severity controls the severity indication of the pci express secondary uncorrectable errors. each bit controls the error ty pe of the corresponding bit in the pci express secondary uncorr ectable error status. 0 = non-fatal: error type is non-fatal. 1 = fatal: error type is fatal. 3 rcvmasev rw 0x0 received master-abort severity 4 reserved_4 rsvd 0x0 reserved 6:5 reserved_6_5 rw 0x2 reserved 7 ucdataerrsev rw 0x0 uncorrectable data error severity 8 ucattrerrsev rw 0x1 uncorrectable attribute error severity 9 ucaddrerrsev rw 0x1 uncorrectable address error severity 10 dtexpsev rw 0x0 delayed transaction discar d timer expired severity 11 perrdetectedsev rw 0x0 pci_perrn assertion severity
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 96 document classification: proprietary information february 27, 2008, preliminary 12 serrdetectedsev rw 0x1 pci_serrn assertion severity 13 internalbrerrsev rw 0x0 internal bridge error severity 31:14 reserved_31_14 rsvd 0x0 reserved table 70: pci uncorrectable error severity register (continued) offset: 0x00134 bit field type/initval description table 71: pci error capability and control register offset: 0x00138 bit field type/initval description 4:0 secucfrsterrptr ro 0x0 pci uncorrectable first error pointer this field reports the bit position of t he first error reported in the pci express secondary uncorrectable error status. this field locks upon receipt of the first uncorrectable error that is not masked. it remains locked until software clears it by writing 1 to the corresponding status bit. upon receipt of the next uncorrectable error that is not masked, the field locks again until cleared as described above. this lock and clear process continues to repeat itself. note: the bits in this field are sticky bits--they are not initialized or modified by reset. 31:5 reserved rsvd 0x0 reserved table 72: pci header log first dword register offset: 0x0013c bit field type/initval description 31:0 shl_transattr ro 0x0 pci header log first dword logs the header of the first error reported in the pci express secondary uncorrectable error status. this field locks upon receipt of the first uncorrectable error that is not masked. it remains locked until software clears it by writing 1 to the corresponding status bit. upon receipt of the next uncorrectable error that is not masked, the field locks again until cleared as described above. this lock and clear process continues to repeat itself. transaction attribute the value transferred on ad[31:0] during the attribute phase. this field is not relevant to conventional pci. this field is hardwired to 0.
88sb2211 register set forward bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 97 table 73: pci header log second dword register offset: 0x00140 bit field type/initval description 3:0 shl_transattr ro 0x0 transaction attribute the value transferred on pci_cbe[3:0]n during the attribute phase. this field is not relevant to conventional pci. this field is hardwired to 0. 7:4 shl_transcmdlow ro 0x0 transaction command lower the 4-bit value transferred on pci_c be[3:0]n during the first address phase. 11:8 shl_transcmdup ro 0x0 transaction command upper the 4-bit value transferred on pci_cbe[3:0]n during the second address phase of a dac transaction. 31:12 reserved rsvd 0x0 reserved table 74: pci header log third dword register offset: 0x00144 bit field type/initval description 31:0 shl_addrlow ro 0x0 transaction address low. the 32-bit value transferred on ad[ 31:0] during the first address phase. table 75: pci header log fourth dword register offset: 0x00148 bit field type/initval description 31:0 shl_addrhigh ro 0x0 transaction address high. the 32-bit value transferred on ad[31:0] during the second address phase. in the case of a 32-bit address, this field is set to zero.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 98 document classification: proprietary information february 27, 2008, preliminary a.4 reverse bridge mode configuration registers the following table provides a summarized list of all of the reverse bridge mode configuration registers, including the re gister names, their type, offset, and a reference to the corresponding table and page for a detailed description of each register and its fields. table 76: register map table for the reverse bridge mode configuration registers register name offset table and page reverse bridge mode configuration header device and vendor id register 0x00000 table 77, p. 99 reverse bridge command and status register 0x00004 table 78, p. 100 class code and revision id register 0x00008 table 79, p. 103 reverse bridge bist header type and cache line size register 0x0000c table 80, p. 104 reverse bridge pci express secondary latency timer and subordinate secondary and primary bus numbers register 0x00018 table 81, p. 104 reverse bridge pci express secondary status i/o limit and i/o base register 0x0001c table 82, p. 105 memory limit and memory base register 0x00020 table 83, p. 106 prefetchable memory limit and prefetchable memory base register 0x00024 table 84, p. 107 prefetchable base upper 32 bits register 0x00028 table 85, p. 108 prefetchable limit upper 32 bits register 0x0002c table 86, p. 108 i/o limit upper 16 bits register and i/o base upper 16 bits 0x00030 table 87, p. 108 capabilities pointer register 0x00034 table 88, p. 109 reverse bridge control interrupt pin and interrupt line register 0x0003c table 89, p. 109 power management capability header register 0x00040 table 90, p. 112 reverse bridge power management control and status register 0x00044 table 91, p. 113 reverse bridge pci express capability register 0x00048 table 92, p. 114 reverse bridge pci express de vice capabilities register 0x0004c table 93, p. 115 reverse bridge pci express device control status register 0x00050 table 94, p. 116 reverse bridge pci express li nk control status register 0x00058 table 95, p. 118 reverse bridge pci express sl ot capabilities register 0x0005c table 96, p. 119 reverse bridge pci express slot control status register 0x00060 table 97, p. 121 reverse bridge pci express root control capabilities register 0x00064 table 98, p. 122 reverse bridge pci express root status register 0x00068 table 99, p. 123 reverse bridge mode device specific gpio control register 0x00074 table 100, p. 124 reverse bridge pci clock output control register 0x00078 table 101, p. 124 reverse bridge prefetch and crs control register 0x00080 table 102, p. 125 marvell diagnostic pci expr ess phy indirect access register 0x000f4 table 103, p. 129
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 99 a.4.1 reverse bridge mode configuration header marvell diagnostic indire ct address register 0x000f8 table 104, p. 129 marvell diagnostic indi rect data register 0x000fc table 105, p. 129 reverse bridge mode exte nded configuration space pci express advanced error report header register 0x00100 table 106, p. 130 pci express uncorrectabl e error status register 0x00104 table 107, p. 130 pci express uncorrectable error mask register 0x00108 table 108, p. 131 pci express uncorrectable error severity register 0x0010c table 109, p. 132 pci express correctable error status register 0x00110 table 110, p. 133 pci express correctable error mask register 0x00114 table 111, p. 134 pci express advanced error capability and control register 0x00118 table 112, p. 135 pci express header log first dword register 0x0011c table 113, p. 135 pci express header log second dword register 0x00120 table 114, p. 135 pci express header log third dword register 0x00124 table 115, p. 136 pci express header log fourth dword register 0x00128 table 116, p. 136 pci uncorrectable error status register 0x0012c table 117, p. 136 reverse bridge pci uncorrectable error mask register 0x00130 table 118, p. 137 pci uncorrectable error severity register 0x00134 table 119, p. 138 pci error capability and control register 0x00138 table 120, p. 139 pci header log first dword register 0x0013c table 121, p. 140 pci header log second dword register 0x00140 table 122, p. 140 pci header log third dword register 0x00144 table 123, p. 141 pci header log fourth dword register 0x00148 table 124, p. 141 table 76: register map table for the reverse bridge mode configuration registers (continued) register name offset table and page table 77: device and vendor id register offset: 0x00000 bit field type/initval description 15:0 venid ro 0x11ab vendor id this field identifies marvell as the vendor of the device. 31:16 devid ro 0x2211 device id
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 100 document classification: proprietary information february 27, 2008, preliminary table 78: reverse bridge command and status register offset: 0x00004 bit field type/initval description 0 ioen rw 0x0 i/o space enable. controls the 88sb2211 response as a ta rget to i/o transactions on the primary interface that address a device that resides behind the bridge. note: software should ensure that outs tanding transactions involving the bridge are completed prior to disabling this bit. 0 = disable: respond to all i/o requests on the primary interface with master abort. forward all i/o transactions fr om the secondary interface to the primary interface. 1 = enable: forwarding of i/o requests to the secondary interface. 1 memen rw 0x0 memory space enable controls the 88sb2211 response as a target to memory accesses on the primary interface that addresses a device t hat resides behind the bridge in both the non-prefetchable and prefetchable memory ranges. note: software should ensure that outs tanding transactions involving the bridge are completed prior to disabling this bit. 0 = disable: respond to all memory requests on the primary interface with master abort. forward all memory requests from the secondary interface to the primary interface. 1 = enable: forwarding of memory tr ansactions to the secondary interface. 2 masen rw 0x0 master enable controls the ability of the 88sb2211 to issue memory and i/o read/write requests on the primary interface. disabl ing this bit prevents the bridge from issuing any memory or i/o read/write requests on the primary interface. when this bit is zero, 88sb2211 disables response as a target to all memory or i/o transactions on the secondary interf ace (they cannot be forwarded to the primary interface). this bit does not affect the issuing of completions on the primary interface or the forwarding of completions. note: software should ensure that outs tanding transactions involving the bridge are completed prior to disabling this bit. 0 = disable: do not initiate memory or i/o transactions on the primary interface and disable response to memory and i/o transactions on secondary interface. 1 = enable: the bridge to operate as a master on the primary interface for memory and i/o transactions forwar ded from the secondary interface. 3 reserved_3 rsvd 0x0 reserved 4 reserved_4 rsvd 0x0 reserved 5 reserved_5 rsvd 0x0 vga palette snoop does not apply to pci express bridges.
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 101 6 perrres rw 0x0 parity error response enable controls the response of the bridge to uncorrectable address, attribute, and data errors on the pci interface. if this bit is set, the bridge takes its normal action when an uncorrectable address, attri bute, or data error is detected. if this bit is cleared, the bridge ignores any uncorrectable address, attribute, and data errors that it detects and conti nue normal operation. the bridge generates parity even if parity error reporting is disabled. also, the bridge forwards poisoned data from conventional pci to pci express as an uncorrectable conventional pci data error, regardless of the setting of this bit. 0 = ignore: uncorrectable address, attribute, and data errors on the secondary interface 1 = enable: uncorrectable address, attribute, and data error detection and reporting on the secondary interface 7 reserved_7 rsvd 0x0 reserved 8 serren rw 0x0 pci_serrn enable this bit enables the assertion of pci_serrn on the pci interface of the 88sb2211. pci_serrn is asserted when any of the following three conditions are true: -reception of fatal, non-fatal, or correctable error messages on the pci express interface masked by see the reverse bridge pci express root control capabilities register, bits [2:0 ] (a dedicated mask bit for each error message type) - the 88sb2211 detects uncorrectable dat a in a special cycle transaction on the pci interface. - the 88sb2211 detects an uncorrectable data error when it is the pci master of a read transaction, and the read was not poisoned tlp on the pci express interface. 0 = disable: pci_serrn assertion on pci interface is disabled. 1 = enable: pci_serrn assertion on pci interface is enabled. 9 prfbtben rw 0x0 fast back-to-back enable controls generation of fast back-to -back transactions on the pci bus. 0 = disable: generation of fast back-to-b ack transactions on the pci interface is disabled. 1 = enable: generation of fast back-to-back transactions on the pci interface is enabled. 10 reserved_10 rsvd 0x0 interrupt disable the 88sb2211 has no internal interrupt resources, and therefore, this bit has no effect. 18:11 reserved_18_11 rsvd 0x0 reserved table 78: reverse bridge command and status register (continued) offset: 0x00004 bit field type/initval description
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 102 document classification: proprietary information february 27, 2008, preliminary 19 reserved_19 rsvd 0x0 interrupt status the 88sb2211 has no internal interrupt resources, and therefore, this bit has no effect. 20 caplist ro 0x1 capability list support this bit indicates that the 88sb2211 c onfiguration header includes capability list. 21 66mhzcap ro 0x1 66 mhz capable 22 reserved_22 rsvd 0x0 reserved 23 fbtbcap ro 0x1 pci fast back-to-back capable. indicates that the 88sb2211 bridge is abl e of responding to fast back-to-back transactions on the pci bus. 24 masdataperr rw1c 0x0 master data parity error this bit is used to report the detection of an uncorrectable data error by the bridge. this bit is set if the bridge is the bus master of the transaction on the pci interface, the bit in the control register is set, and either of the following two conditions occur: - the bridge asserts pci_perrn on a read transaction. - the bridge detects pci_perrn asserted on a write transaction. if the bit is set to zero, this bit is not set when an error is detected. 26:25 devseltim ro 0x1 pci_devseln timing indicates the 88sb2211 device?s pci_devseln timing as medium. this bit is hardwired to 1. 27 starabort rw1c 0x0 signaled target abort this bit reports the signaling of a tar get-abort termination by the 88sb2211 when it responds as the target of a transaction on its pci interface. 28 rtabort rw1c 0x0 received target abort this bit reports the detection of a target-abort termination by the 88sb2211 when it is the master of a transaction on its pci interface. 29 rmabort rw1c 0x0 received master abort. this bit reports the detection of a master-abort termination by the 88sb2211 when it is the master of a transaction on its pci interface. table 78: reverse bridge command and status register (continued) offset: 0x00004 bit field type/initval description
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 103 30 ssyserr rw1c 0x0 signalled system error this bit reports the assertion of pci_serrn on the pci interface of the 88sb2211. this bit is not set if the field in this register is de-asserted. 0 = not asserted: pci_serrn was not asserted on pci interface. 1 = asserted: pci_serrn was asserted on pci interface. 31 detparerr rw1c 0x0 detected parity error this bit reports the detection of an uncor rectable address, attribute, or data error by the 88sb2211 on its pci interface. this bit must be set when any of the following three conditions are true: - the 88sb2211 detects an uncorrectable address error as a potential target. -the 88sb2211 detects an uncorrectable data error when it is the target of a write transaction. - the 88sb2211 detects an uncorrectable data error when it is the pci master of a read transaction note: the bit is set regardless of the state of the bit in this register. 0 = not_detected: uncorrectable address, attribute, or data error not detected on pci interface 1 = detected: uncorrectable address, attribute, or data error detected on pci interface table 78: reverse bridge command and status register (continued) offset: 0x00004 bit field type/initval description table 79: class code and revision id register offset: 0x00008 bit field type/initval description 7:0 revid ro 0x1 88sb2211 revision number 15:8 progif ro 0x0 register level programming interface 23:16 subclass ro 0x04 88sb2211 sub class -- pci-to-pci bridge 31:24 baseclass ro 0x06 88sb2211 base class -- bridge device
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 104 document classification: proprietary information february 27, 2008, preliminary table 80: reverse bridge bist header type and cache line size register offset: 0x0000c bit field type/initval description 7:0 cacheline rw 0x00 88sb2211 cache line size this field specifies the system cac he line size in units of dwords. the value in this register is used by the 88sb2211 for the following purposes: 1. to determine the pci interface command type when forwarding memory read transactions from t he pci express interface. 2. to determine the read transactions pref etch size of the pci when acting as target. 8 = 32 bytes prefetch 16 = 64 bytes prefetch 32 = 128 bytes prefetch 15:8 prlattimer rw 0x0 pci latency timer specifies (in pci clock units) the value of the latency timer value of the 88sb2211. used by pci master when acting as a requester. 23:16 headtype ro 0x01 88sb2211 configuration header type type 1 single-function configuration header. 31:24 bist ro 0x00 built-in self test (bist) the 88sb2211 does not support bist. table 81: reverse bridge pci express secondary latency timer and subordinate secondary and primary bus numbers register offset: 0x00018 bit field type/initval description 7:0 primbusnm rw 0x0 primary bus number 15:8 secbusnm rw 0x0 secondary bus number used for type 1 configuration access handling. 23:16 subbusnm rw 0x0 subordinate bus number used for type 1 configuration access handling. 31:24 reserved_31_24 rsvd 0x0 secondary latency timer does not apply to pci express.
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 105 table 82: reverse bridge pci express secondary status i/o limit and i/o base register offset: 0x0001c bit field type/initval description 3:0 iobasetype ro 0x1 i/o base type indicates that the 88sb2211 supports 32-bit i/o addressing. 7:4 iobase rw 0x0 i/o base defines the bottom address of the i/o address range that determines when to forward i/o transactions from one interface to the other. the upper 4 bits are writable and correspond to address bits [15:12]. the lower 12 bits are assumed to be 000h. the 16 bits corresponding to address bits [31:16] of the i/o address are defined in the i/o limit upper 16 bits register and i/o base upper 16 bits. 11:8 iolimittype ro 0x1 i/o limit type indicates that the 88sb2211 supports 32-bit i/o addressing. 15:12 iolimit rw 0x0 i/o limit defines the top address of the i/o address range that determines when to forward i/o transactions from one interface to the other. the upper 4 bits are writable and correspond to address bits [15:12]. the lower 12 bits are assumed to be fffh. the 16 bits corresponding to address bits [31:16] of the i/o address are defined in the i/o limit upper 16 bits register and i/o base upper 16 bits. note: if there are no i/o addresses on the secondary side of the bridge, this field can be programmed to a smaller value than the field. in that case, the bridge does not forward any i/o transactions from the primary interface to the secondary, and does forward all i/o transactions from the secondary interface to the primary interface. note: 20:16 reserved_20_16 rsvd 0x0 reserved 21 66mhzcap rsvd 0x0 secondary 66 mhz capable does not apply to pci express devices. 22 reserved_22 rsvd 0x0 reserved 23 fbtbcap rsvd 0x0 secondary fast back-to-back transactions capable does not apply to pci express devices. 24 datapar rw1c 0x0 master data parity error reports detection of uncorrectable data errors by the 88sb2211. this bit is set when bit[16] of reverse bridge control interrupt pin and interrupt line register is set and either of the following occur: - the 88sb2211 receives a poisoned comp letion on the pci express interface. - the 88sb2211 transmits a poisoned write request on the pci express interface.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 106 document classification: proprietary information february 27, 2008, preliminary 26:25 devseltim rsvd 0x0 secondary pci_devseln timing does not apply to pci express. 27 starabort rw1c 0x0 signaled target abort this bit is set when the 88sb2211 generates a completion with completer abort completion status in response to a request received on the pci express interface. 28 rtabort rw1c 0x0 received target abort this bit is set when the 88sb2211, as a requester (master), receives a completion with the status completer abort. 29 rmabort rw1c 0x0 received master abort this bit is set when the 88sb2211 re ceives a completion with unsupported request completion status on the pci express interface. 30 rsyserr rw1c 0x0 received system error this bit is set when the 88sb2211 receives an err_fatal or err_nonfatal message. this bit is not set if the field of command and status register is not set. 31 detparerr rw1c 0x0 detected parity error this bit is set when the 88sb2211 receives a poisoned tlp on the pci express interface. note: the bit is set regardless of the state of the bit in this register. table 82: reverse bridge pci express secondary status i/o limit and i/o base register (continued) offset: 0x0001c bit field type/initval description table 83: memory limit and memory base register offset: 0x00020 bit field type/initval description 3:0 reserved ro 0x0 this bit is hardwired to 0. 15:4 membase rw 0x0 memory base defines the bottom address of the memory address range that determines when to forward memory transactions from one interface to the other. these bits correspond to address bits [31:20] in the memory address. the lower 20 bits are assumed to be 00000h
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 107 19:16 reserved ro 0x00 this bit is hardwired to 0. 31:20 memlimit rw 0x0 memory limit defines the top address of the memory address range that determines when to forward memory transactions from one interface to the other. these bits correspond to address bits [31:20] in the memory address. the lower 20 bits are assumed to be fffffh. note: if there are no memory-mapped i/o addresses on the secondary side of the bridge, the fiel d must be programmed to a smaller value than the field. if there is no prefetchable memory, and there is no memory-mapped i/o on the secondary side of the bridge, then the bridge does not forward any memory transactions from the primary bus to the secondary, and does forward all memory transactions from the secondary bus to the primary bus. note: table 83: memory limit and memory base register (continued) offset: 0x00020 bit field type/initval description table 84: prefetchable memory limit and prefetchable memory base register offset: 0x00024 bit field type/initval description 3:0 perbasetype ro 0x1 prefetchable memory base type indicates that the 88sb2211 supports 64-bit prefetchable memory addressing. 15:4 prebase rw 0x0 prefetchable memory base defines the bottom address of the prefetchable memory address range that determines when to forward memory transactions from one interface to the other. these bits correspond to address bits [31:20] in the memory address. the lower 20 bits are assumed to be 00000h. the prefetchable base address upper 32-bit register specifies the bit [63: 32] of the 64-bit prefetchable memory address. 19:16 prelimittype ro 0x1 prefetchable memory limit defines the top address of the prefetchable memory address range that determines when to forward memory transactions from one interface to the other. these bits correspond to address bits [31:20] in the memory address. the lower 20 bits are assumed to be fffffh. the prefetchable-limit upper 32-bit register specifies the bit [63:32] of the 64-bit prefetchable memory address. note: if there is no prefetchable memory, and there is no memory-mapped i/o on the secondary side of the bridge, then the bridge does not forward any memory transactions from the primary bus to the secondary, and does forward all memory transactions from the secondary bus to the primary bus. note:
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 108 document classification: proprietary information february 27, 2008, preliminary 31:20 prelimit rw 0x0 prefetchable memory limit defines the top address of the memory address range that determines when to forward memory transactions from one interface to the other. these bits correspond to address bits [31:20] in the memory address. the lower 20 bits are assumed to be fffffh. note: if there is no prefetchable memory, and there is no memory-mapped i/o on the secondary side of the bridge, then the bridge does not forward any memory transactions from the primary bus to the secondary, and does forward all memory transactions from the secondary bus to the primary bus. note: table 84: prefetchable memory li mit and prefetchable memory base register (continued) offset: 0x00024 bit field type/initval description table 85: prefetchable base upper 32 bits register offset: 0x00028 bit field type/initval description 31:0 prebaseup rw 0x0 prefetchable memory-base upper 32 bits defines the upper 32 bits of the bottom address of the prefetchable memory address range that determines when to fo rward memory transactions from one interface to the other. table 86: prefetchable limit upper 32 bits register offset: 0x0002c bit field type/initval description 31:0 prelimitup rw 0x0 prefetchable memory-limit upper 32 bits. defines the upper-limit of the 64-bit prefetchable memory address range that determines when to forward memory transactions from one interface to the other. table 87: i/o limit upper 16 bits register and i/o base upper 16 bits offset: 0x00030 bit field type/initval description 15:0 iobaseup rw 0x0 i/o base upper 16 bits defines the upper 16 bits of the bottom address of the i/o address range that determines when to forward i/o transactions from one interface to the other. 31:16 iolimitup rw 0x0 i/o limit upper 16 bits defines the upper-limit address of the 32-bit i/o memory address range that determines when to forward i/o transactions from one interface to the other.
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 109 table 88: capabilities pointer register offset: 0x00034 bit field type/initval description 7:0 capptr ro 0x40 capability list pointer the current value in this field points to the pci power management capability set in power management capability header at offset 0x40. 31:8 reserved rsvd 0x0 reserved table 89: reverse bridge control interrupt pin and interrupt line register offset: 0x0003c bit field type/initval description 7:0 intline rw 0x0 provides interrupt line routing information. 15:8 intpin ro 0x0 indicates that the 88sb2211 does no t implement a virtual interrupt pin. 16 secperrresen rw 0x0 secondary parity error response enable this bit controls the 88sb2211?s setti ng of the secondary status bit[24] in response to a received pois oned data error as a requester (master) on the pci express port. note: the setting of this bit does not affect the secondary status bit. 17 secserren rw 0x0 secondary pci_serrn enable controls the forwarding of secondary interface reception of err_fatal or err_nonfatal messages to pci_serrn assertions on the pci interface. the bridge asserts pci_serrn on the pci bus only if the is set in the command register. 0 = disable: the forwarding of secondary interface reception of err_fatal or err_nonfatal messages to pci_serrn assertions on the pci interface. 1 = enable: the forwarding of secondary interface reception of err_fatal or err_nonfatal messages to pci_serrn assertions on the pci interface.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 110 document classification: proprietary information february 27, 2008, preliminary 18 isaen rw 0x0 isa enable controls the response of the bridge to isa i/o addresses. this applies only to i/o addresses that are enabled by the i/o base and i/o limit registers and are in the first 64 kb of pci i/o address space (0000 0000h to 0000 ffffh). if this bit is set, the bridge blocks any forwar ding from primary to secondary of i/o transactions addressing the last 768 byte s in each 1-kb block. in the opposite direction (secondary to primary), i/o tr ansactions are forwarded if they address the last 768 bytes in each 1-kb block. 0 = downstream: forward downstream all i/o addresses in the address range defined by the i/o base and i/o limit registers. 1 = upstream: forward upstream isa i/o addresses in the address range defined by the i/o base and i/o limit r egisters that are in the first 64 kb of the pci i/o address space (top 768 bytes of each 1-kb block). 19 vgaen rw 0x0 vga enable controls the response of the bridge to vg a-compatible addresses. if this bit is set, the bridge forwards the following ac cesses on the primary interface to the secondary interface (and, conversely , blocks the forwarding of these addresses from the secondary to the primary interface): - memory accesses in the range 000a 0000h to 000b ffffh - i/o addresses in the first 64 kb of t he i/o address space (address[31:16] for pci express are 0000h) and where address[9:0] is in the range of 3b0h to 3bbh or 3c0h to 3dfh (inclusive of isa address aliases). address[15:10] may possess any value and is not used in the decoding. if the vga enable bit is set, forwarding of vga addresses is independent of the value of the isa enable bit (located in the bridge control, interrupt pin and interrupt line), the i/o address range and memory address ranges defined by the i/o limit upper 16 bits register and i/o base upper 16 bits, the memory limit and memory base, and the prefet chable memory limit and prefetchable memory base of the bridge. the forwardi ng of vga addresses is qualified by the and bits in the command and status. 0 = donotforward: vga compatible memory and i/o addresses from the primary to the secondary interface (addresses defined above) unless they are enabled for forwarding by the defined i/o and memory address ranges. 1 = forward: vga compatible memory and i/o addresses (addresses defined above) from the primary interface to the secondary interface (if the and bits are set) independent of the i/o and memory address ranges and independent of the bit in this register. 20 vga16bitdec rw 0x0 vga 16-bit decode this bit enables the bridge to prov ide 16-bit decoding of vga i/o address precluding the decoding of alias addres ses every 1 kb. this bit only has meaning if the vga enable bit in this regist er is also set to 1, enabling vga i/o decoding and forwarding by the bridge. this read/write bit enables system configuration software to select between 10- and 16-bit i/o address decoding for all vga i/o register accesses that are forwarded from primary to secondary whenever the vga enable bit is set to 1. 0 = 10-bit_address: execute 10-bit add ress decodes on vga i/o accesses. 1 = 16-bit_address: execute 16-bit add ress decodes on vga i/o accesses. table 89: reverse bridge control interrupt pin and interrupt line register (continued) offset: 0x0003c bit field type/initval description
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 111 21 mamode rw 0x0 master-abort mode controls the behavior of a bridge when it receives a master-abort termination (e.g., an unsupported request on pci express) on either interface. 0 = donotreport: master-aborts. when a ur response is received from pci express for non-posted transactions, return ffff ffffh on reads and complete i/o writes normally. when a master-abort is received on the pci interface for posted transactions initiated from the pci express interface, no action is taken (i.e., all data is discarded). when a master-abort is received on the pci interface for non-posted transactions initiated from the pci express interface, the 88sb2211 completes it as an unsupported request. 1 = report: ur completions from pci ex press by signaling target-abort on the pci interface. for posted transactions initiated from the pci express interface and master-aborted on the pci interface, the bridge asserts pci_serrn (provided the bit is set in the command and status). when a master-abort is received on the pci interface for non-posted transactions initiated from the pci express interface, the 88sb2211 completes it as an unsupported request. 22 secbusrst rw 0x0 secondary bus reset forces the assertion of rst_out or the transmission of hot reset on the pci express interface to the end point. -if the pci express link state is l2/l3 rst_out is asserted to the endpoint. -in all other cases hot reset is sent to the endpoint. 0 = donotforce: assertion of rst_outn is not forced. 1 = force: assertion of rst_outn is forced. 23 scfbtben rsvd 0x0 secondary fast-back-to-back enable does not apply to pci express devices. 24 prdt rw 0x0 primary discard timer controls the number of pci clock cycles that the bridge waits for a master on the pci interface to repeat a delayed transaction request. the counter starts once the completion (pci express comp letion associated with the delayed transaction request) has reached the head of the upstream queue of the bridge (i.e., all ordering requirements have been satisfied and the bridge is ready to complete the delayed transaction with the originating master on the primary bus). if the originating master does not repeat the transaction before the counter expires, the bridge deletes the delayed transaction from its queue and set the discard timer status bit. 0 = 2^15_pci: the primary discard ti mer counts 2^15 pci clock cycles. 1 = 2^10_pci: the primary discard timer counts 2^10 pci clock cycles. 25 secdt rsvd 0x0 secondary discard timer does not apply to pci express devices. table 89: reverse bridge control interrupt pin and interrupt line register (continued) offset: 0x0003c bit field type/initval description
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 112 document classification: proprietary information february 27, 2008, preliminary 26 dtstt rw1c 0x0 discard timer status this bit is set to a 1 when the pc i discard timer expires and a delayed completion is discarded from a queue in the bridge. 0 = no_discard: timer error 1 = discard: timer error 27 dtserren rw 0x0 discard timer pci_serrn enable this bit enables the bridge to generate pci_serrn assertion on pci interface when the pci discard timer expires and a delayed transaction is discarded from a queue in the bridge. 0 = donotassert: pci_serrn on the pci interface as a result of the expiration of the pci discard timer. 1 = assert: pci_serrn on the pci interf ace if the pci discard timer expires and a delayed transaction is discarded from a queue in the bridge. 31:28 reserved rsvd 0x0 reserved table 89: reverse bridge control interrupt pin and interrupt line register (continued) offset: 0x0003c bit field type/initval description table 90: power management capability header register offset: 0x00040 bit field type/initval description 7:0 capid ro 0x01 capability id current value identifies the pci power management capability. 15:8 nextptr ro 0x48 next item pointer current value points to pci express capability. 18:16 pmcver ro 0x2 pci power management capability version 20:19 reserved ro 0x0 pme clock does not apply to pci express. this field is hardwired to 0. 21 dsi ro 0x0 device specific initialization the 88sb2211 does not requires device specific initialization. 24:22 auxcur ro 0x1 auxiliary current requirements the 88sb2211 does not require current from vaux in d3cold state. 25 d1sup ro 0x1 d1 support the 88sb2211 supports d1 power management state.
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 113 26 d2sup ro 0x1 d2 support the 88sb2211 supports d2 power management state. 31:27 pmesup ro 0x1f power management event (pme) support the 88sb2211 supports pme generation from d0, d1, d2, d3cold power management states. table 90: power management capability header register (continued) offset: 0x00040 bit field type/initval description table 91: reverse bridge power management control and status register offset: 0x00044 bit field type/initval description 1:0 pmstate rw 0x0 power state this field controls the power management state of the 88sb2211. the device supports all power management states. when writing d3, the read value from this fi eld is the previous value, only after the pci express link is in l2/l3 state does the read value move to d3 state. note: a transition from state d3 to state d0 causes an internal reset. in states d1, d2 and d3hot, pci memory and i/o accesses are disabled, as well as the interrupt emulation mess ages, and only configuration cycles are allowed. 0 = d0 1 = d1 2 = d2 3 = d3 7:2 reserved_7_2 rsvd 0x0 reserved 8 pme_en rw 0x0 pme enable controls pm_pme message generation. note: power on sticky bit--not initialize d by either fundamental or hot reset. 0 = disabled 1 = enabled 12:9 pmdatasel ro 0x0 data select data register is not implemented. 14:13 pmdatascale ro 0x0 data scale data register is not implemented.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 114 document classification: proprietary information february 27, 2008, preliminary 15 pme_stat rw1c 0x0 this bit is set whenever pci_pmen is asserted on pci bus. these are the scenarios which will lead to pci_pmen assertion: 1. pci express pme message is received. 2. pci express waken signal is asserted. this bit can be set only if is set. note: power on sticky bit--not initializ ed by either fundamental or hot reset. 21:16 reserved_21_16 rsvd 0x0 reserved 22 b2b3sup ro 0x1 b2_b3 support for d3hot shutting down, the pci express clock is not supported for d2 and d3hot by default. when cleared, indicates that, when the 88sb2211 is programmed to d3hot, its secondary bus has its power removed, and its pci express clocks are stopped (b3). this bit is only meaningful if the bit is set. 23 bpccen ro 0x1 bus power/clock control enable when set, indicates that the bus power/c lock control mechanism, as defined in section 4.7.1 of the pci power m anagement specification 1.1, is enabled. the bstate and the secondary clocks are controlled accordingly. note: to disable the bus power clock cont rol, this field should be set to 0x0 via the twsi serial initialization process. (this bit can be written from the twsi port). note: shutting down the pci express clock out for power management events by default is not enabled. 31:24 pmdata ro 0x0 power management data data register is not implemented. table 91: reverse bridge power management control and status register (continued) offset: 0x00044 bit field type/initval description table 92: reverse bridge pci express capability register offset: 0x00048 bit field type/initval description 7:0 capid ro 0x10 capability id the current value of this field identifies the pci express capability. 15:8 nextptr ro 0x0 next item pointer the current value of this field points to the end of the capability list (null).
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 115 19:16 capver ro 0x1 capability version this field indicates the pci express base spec 1.0a version of the pci-express capability. 23:20 devtype ro 0x8 device/port type pci/pci-x to pci express bridge 24 slotimp ro 0x1 slot implemented 29:25 intmsgnum ro 0x0 interrupt message number this bit is hardwired to 0. 31:30 reserved rsvd 0x0 reserved table 92: reverse bridge pci express capability register (continued) offset: 0x00048 bit field type/initval description table 93: reverse bridge pci express device capabilities register offset: 0x0004c bit field type/initval description 2:0 maxpldsizesup ro 0x0 maximum payload size supported 128b mps support. this bit is hardwired to 0. 4:3 phntmfncsup ro 0x0 phantom functions support phantom functions are not supported. this bit is hardwired to 0. 5 exttagsup ro 0x0 extended tag field support extended tag is not supported. this bit is hardwired to 0. 11:6 reserved_11_6 rsvd 0x0 reserved 12 attbutprs ro 0x0 attention button present the 88sb2211 does not support attention button. this bit is hardwired to 0. 13 attindprs ro 0x0 attention indicator present the 88sb2211 does not support attention indicator this bit is hardwired to 0.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 116 document classification: proprietary information february 27, 2008, preliminary 14 pwrindprs ro 0x0 power indicator present the 88sb2211 does not support attention indicator. this bit is hardwired to 0. 15 role-based error reporting ro 0x0 the 88sb2211 does not support role based error reporting. 31:16 reserved_31_16 rsvd 0x0 reserved table 93: reverse bridge pci express device capabilities register (continued) offset: 0x0004c bit field type/initval description table 94: reverse bridge pci express device control status register offset: 0x00050 bit field type/initval description 2:0 reserved_2_0 rw 0x0 reserved 3 urrepen rw 0x0 unsupported request (ur) reporting enable controls error reporting on behalf of unsupported request errors detected on the pci express interface only. note: ur related pci_serrn assertion is still enabled when urrepen=0, if the bit in the command and status is set. 0 = masked: ur related error messages are masked. status bit is not masked. 1 = enabled: ur related error messages enabled. 4 enro ro 0x0 enable relaxed ordering the 88sb2211 never sets the relaxed ordering attribute in transactions it initiates as a requester. this bit is hardwired to 0. 7:5 maxpldsz rw 0x0 maximum payload size the maximum payload size supported is 128b (refer to bit in the pci express device capabilities). 0 = 128b 1-7 = reserved 8 reserved_8 ro 0x0 extended tag field enabled not supported. this bit is hardwired to 0. 9 reserved_9 ro 0x0 phantom function enable not supported. this bit is hardwired to 0.
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 117 10 auxpwren rw 0x0 auxiliary (aux) power pm enable controls allocation of aux power to the device. note: power on reset sticky bit is not initialized by either fundamental or hot reset. 0 = disabled: vaux is not allocated. 1 = enabled: vaux is allocated. 11 enns ro 0x0 enable no snoop the 88sb2211 never sets the no snoop attribute in transactions it initiates as a requester. this bit is hardwired to 0. 14:12 maxrdrqsz rw 0x2 maximum read request size this field limits the 88sb2211 maxi mum read request size as a requestor (master). 0 = 128b 1 = 256b 2 = 512b 3 = 1_kb 4 = 2_kb 5 = 4_kb 15 brcrsen rw 0x0 bridge configuration retry enable when the 88sb2211 is configured to root -complex, this bit is not relevant. 16 corerrdet rw1c 0x0 correctable error detected this bit indicates the status of t he correctable errors detected by the 88sb2211. it set for the corresponding errors on both the pci express and conventional pci interfaces. 17 nferrdet rw1c 0x0 non-fatal error detected this bit indicates the status of the n on-fatal errors detected by the 88sb2211. it is set for the corresponding errors on both the pci express and conventional pci interfaces. 18 ferrdet rw1c 0x0 fatal error detected this bit indicates the status of the fatal errors detected by the 88sb2211. it is set for the corresponding errors on both the pci express and conventional pci interfaces. 19 urdet rw1c 0x0 unsupported request detected this bit indicates that the 88sb 2211 receives an unsupported request. it is set for the corresponding errors on both the pci express and conventional pci interfaces. table 94: reverse bridge pci express device control status register (continued) offset: 0x00050 bit field type/initval description
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 118 document classification: proprietary information february 27, 2008, preliminary 20 auxpwrdet ro 0x0 aux power detected indicates that the 88sb2211 detected aux power. 21 transpend ro 0x0 transactions pending the 88sb2211 does not issue non-posted requests on its own behalf. this bit is hardwired to 0. 31:22 reserved_31_22 rsvd 0x0 reserved table 94: reverse bridge pci express device control status register (continued) offset: 0x00050 bit field type/initval description table 95: reverse bridge pci express link control status register offset: 0x00058 bit field type/initval description 1:0 aspm_cnt rw 0x0 active state link pm control this field controls the level of ac tive state pm supported on the link. 0 = disabled 1 = l0s_entry_supported 2 = reserved 3 = l0s_l1_entry_supported 2 reserved_2 rsvd 0x0 reserved 3 rcb ro 0x0 read completion boundary not applicable to the 88sb2211. this bit is hardwired to 0. 4 lnkdis rw 0x0 link disable activation procedure: 1. set this bit to trigger link disable. 2. poll de-assertion (pci expr ess status register, bit 0) ensure the link is disabled. 3. clear the bit to exit to detect and enable the link again. 5 retrnlnk rw 0x0 retrain link this bit forces the device to initiate link retraining. always returns 0 when read. 6 cmnclkcfg rw 0x0 common clock configuration when set by software, this bit indicate s that both devices on the link use a distributed common reference clock.
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 119 7 extdsnc rw 0x0 extended sync when set, this bit forces extended transmission of 4096 fts ordered sets followed by a single skip ordered set in exit from l0s and extra (1024) ts1 at exit from l1. note: this bit is used for test and measurement only. note: 15:8 reserved_15_8 rsvd 0x0 reserved 19:16 lnkspd ro 0x1 link speed the only link speed available is 2.5 gbps. 0 = reserved 1 = 2.5 gbps 2-15 = reserved the value of this field is un defined when the link is not up. 25:20 neglnkwdth ro 0x0 negotiated link width the only link width available is x1. 0 = reserved 1 = x1 2-63 = reserved the value of this field is un defined when the link is not up. 26 reserved_26 ro 0x0 reserved 27 lnktrn ro 0x0 link training this bit indicates that link training is in progress. this bit is cleared once li nk training is complete. 28 sltclkcfg ro 0x1 slot clock configuration . 0 = independentclock: the 88sb 2211 uses an independent clock, irrespective of the presence of a reference clock on the connector. 1 = referenceclock: the 88sb2211 uses the reference clock that the platform provides. 31:29 reserved_31_29 rsvd 0x0 reserved table 95: reverse bridge pci express link control status register (continued) offset: 0x00058 bit field type/initval description table 96: reverse bridge pci expr ess slot capabilities register offset: 0x0005c bit field type/initval description 0 attention button present ro 0x0 reserved - not supported
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 120 document classification: proprietary information february 27, 2008, preliminary 1 power controller present ro 0x0 reserved - not supported 2 mrl sensor present ro 0x0 reserved - not supported 3 attention indicator present ro 0x0 reserved - not supported 4 power indicator present ro 0x0 reserved - not supported 5 hot-plug surprise ro 0x0 reserved - not supported 6 hot-plug capable ro 0x0 reserved - not supported 14:7 slot power limit value rw 0x19 in combination with the slot powerlimit scale value, specifies the upper limit on power supplied by slot. power limit (in watts) calculated by mult iplying the value in this field by the value in the slot power limit scale fi eld except when the slot power limit scale field equals 00b (1.0x) and slot power limit value exceeds 239, the following alternativ e encodings are used: 240 = 250 w slot power limit 241 = 275 w slot power limit 242 = 300 w slot power limit 243-255 = reserved writes to this register also cause the 88sb2211 to send the set_slot_power_limit message. 16:15 slot power limit scale rw 0x0 slot power limit scale specif ies the scale used for the slot power limit value. writes to this register also cause the 88sb2211 to send the set_slot_power_limit message. 0 = 00: 1.0x 1 = 01: 0.1x 2 = 10: 0.01x 3 = 11: 0.001x 17 electromechanical interlock present ro 0x0 reserved - not supported 18 no command completed support ro 0x0 reserved - not supported 31:19 physical slot number ro 0x0 reserved - not supported table 96: reverse bridge pci express slot capabilities register (continued) offset: 0x0005c bit field type/initval description
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 121 table 97: reverse bridge pci express slot control status register offset: 0x00060 bit field type/initval description 0 attention button pressed enable ro 0x0 reserved - not supported 1 power fault detected enable ro 0x0 reserved - not supported 2 mrl sensor changed enable ro 0x0 reserved - not supported 3 presence detect changed enable ro 0x0 reserved - not supported 4 command completed interrupt enable ro 0x0 reserved - not supported 5 hot-plug interrupt enable ro 0x0 reserved - not supported 7:6 attention indicator control ro 0x0 reserved - not supported 9:8 power indicator control ro 0x0 reserved - not supported 10 power controller control ro 0x0 reserved - not supported 11 electromechanical interlock control ro 0x0 reserved - not supported 12 data link layer state changed enable ro 0x0 reserved - not supported 15:13 reserved rsvd 0x0 reserved 16 attention button pressed ro 0x0 reserved - not supported 17 power fault detected ro 0x0 reserved - not supported
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 122 document classification: proprietary information february 27, 2008, preliminary 18 mrl sensor changed ro 0x0 reserved - not supported 19 presence detect changed ro 0x0 reserved - not supported 20 command completed ro 0x0 reserved - not supported 21 mrl sensor state ro 0x0 reserved - not supported 22 presence detect state ro 0x1 reserved - not supported 23 electromechanical interlock status ro 0x0 reserved - not supported 24 data link layer state changed ro 0x0 reserved - not supported 31:25 reserved_31_25 rsvd 0x0 reserved table 97: reverse bridge pci express slot control status register (continued) offset: 0x00060 bit field type/initval description table 98: reverse bridge pci express root control capabilities register offset: 0x00064 bit field type/initval description 0 system error on correctable error enable rw 0x0 if set, this bit indicates that a system error should be generated if a correctable error (err_cor) is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself. the mechanism for signaling a system error to the system pci_serrn assertion on the pci bus. note: pci_serrn is asserted on pci bus only if both serren bit of command register and secserren of bridge control register are enabled. note: 1 system error on non-fatal error enable rw 0x1 if set, this bit indicates that a system error should be generated if a non-fatal error (err_nonfatal) is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself. the mechanism for signaling a system error to the system pci_serrn assertion on the pci bus. note: pci_serrn is asserted on the pci bus only if both bit of the command register and the bit of the of bridge control register are enabled. note:
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 123 2 system error on fatal error enable rw 0x1 if set, this bit indicates that a system error should be generated if a fatal error (err_fatal) is reported by any of t he devices in the hierarchy associated with this root port, or by the root port itself. the mechanism for signaling a system error to the system pci_serrn assertion on the pci bus. note: pci_serrn is asserted on pci bus only if both bit of command register and secserren of bridge control register are enabled. note: 3 pme interrupt enable rw 0x0 when set, this bit enables interrupt generation upon receipt of a pme message as reflected in the pme status bit, in reverse bridge mode configuration register. 4 crs software visibility enable ro 0x0 reserved - not supported. 15:5 reserved_15_5 rsvd 0x0 reserved 16 crs software visibility ro 0x0 reserved - not supported. 31:17 reserved_31_17 rsvd 0x0 reserved table 98: reverse bridge pci express root control capabilities register (continued) offset: 0x00064 bit field type/initval description table 99: reverse bridge pci express root status register offset: 0x00068 bit field type/initval description 15:0 pme requester id ro 0x0 this field indicates the pci requester id of the last pm_pme requester. this field is only valid when the pme status is set. 16 pme status rw1c 0x0 this bit indicates that pm_pme me ssage was sent by the pme requester indicated in the pme requester id field. subsequent pmes are kept pending until the status register is cleared by software by writing a 1b. 17 pme pending ro 0x0 this bit indicates that one more pme is pending. 18 pme_to_ack_rcv rw1c 0x0 set if pme_to_ack message was received. 31:19 reserved_31_19 rsvd 0x0 reserved
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 124 document classification: proprietary information february 27, 2008, preliminary a.4.2 reverse bridge mode device specific table 100: gpio control register offset: 0x00074 bit field type/initval description 7:0 gpioouten rw 0x0 general purpose i/o output enable controls the direction of the gpio si gnal. by default all gpio pins are inputs. note: gpioouten[n] controls gpio[n] pin, n=0..7 0 = input 1 = output 15:8 gpiodataout rw 0x0 general purpose i/o data out controls the data driven on the gpio pins, when configured as an output by the field. note: gpiodataout[n] controls gpio[n] pin, n=0..7 23:16 gpiodatain ro 0x0 general purpose i/o data in reads the current state of the gpio pin. valid only when gpio pin is configured as an input by the field. note: gpiodatain[n] reads gpio[n] pin, n=0..7 31:24 reserved rsvd 0x0 reserved table 101: reverse bridge pci clock output control register offset: 0x00078 bit field type/initval description 0 clockoutdis0 rw sar pci clock out 0 disable controls the activation of pci_clk_out[0]. when set, pci_clk_out[0] is driven to 0. 0 = enabled: pci clock enabled 1 = disabled: pci clock disabled 1 clockoutdis1 rw 0x1 pci clock out 1 disable controls the activation of pci_clk_out[1]. when set, pci_clk_out[1] is driven to 0. 0 = enabled: pci clock enabled 1 = disabled: pci clock disabled 2 clockoutdis2 rw 0x1 pci clock out 2 disable controls the activation of pci_clk_out[2]. when set, pci_clk_out[2] is driven to 0. 0 = enabled: pci clock enabled 1 = disabled: pci clock disabled
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 125 3 clockoutdis3 rw 0x1 pci clock out 3 disable controls the activation of pci_clk_out[3]. when set, pci_clk_out[3] is driven to 0. 0 = enabled: pci clock enabled 1 = disabled: pci clock disabled 4 clockoutdis4 rw 0x1 pci clock out 4 disable controls the activation of pci_clk_out[4]. when set, pci_clk_out[4] is driven to 0. 0 = enabled: pci clock enabled 1 = disabled: pci clock disabled 5 clockoutdis5 rw 0x1 pci clock out 5 disable controls the activation of pci_clk_out[5] when set, pci_clk_out[5] is driven to 0. 0 = enabled: pci clock enabled 1 = disabled: pci clock disabled 31:6 reserved rsvd 0x0 reserved table 101: reverse bridge pci clock output control register (continued) offset: 0x00078 bit field type/initval description table 102: reverse bridge prefetch and crs control register offset: 0x00080 bit field type/initval description 1:0 mrmprftchmd rw 0x3 read multiple prefetch mode 0 = prefetch_disabled 1 = prefetch_enabled 2 = reserved 3 = aggressive_prefetch_enabled 2 mrmaggrinitwm rw 0x1 memory read multiple aggressive prefetch initial read water mark controls the number of 128-bytes buffers to be pre-fetched initially. note: relevant only if aggressive prefetch is enabled by the bit. 0 = two: the 88sb2211 pre-fetches two 128-bytes buffers initially. 1 = three: the 88sb2211 pre-fetches three 128-bytes buffers initially.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 126 document classification: proprietary information february 27, 2008, preliminary 5:3 mrmaggrnextwm rw 0x0 memory read multiple aggressive prefetch next read watermark controls the criteria for issuing the next prefetch read request on the pci express interface. note: relevant only if aggressive prefetch is enabled by the bit. 0 = one data cycle: fetch next buffer after one data cycle is driven on the bus. 1 = two data cycles: fetch next buffer after two data cycles are driven on the bus. 2 = three data cycles: fetch next buffer after three data cycles are driven on the bus. 3 = four data cycles: fetch next buffer after four data cycles are driven on the bus. 4 = five data cycles: fetch next buffer af ter five data cycles are driven on the bus. 5 = six data cycles: fetch next buffer af ter six data cycles are driven on the bus. 6 = seven data cycles: fetch next buffer after seven data cycles are driven on the bus. 7 = eight data cycles: fetch next buffer after eight data cycles are driven on the bus. 6 mrmaggrreswm rw 0x0 memory read multiple aggressive prefetch response watermark controls the criteria for responding to the delayed read on the pci bus. note: relevant only if aggressive prefetch is enabled by the bit. 0 = one: the 88sb2211 drives read dat a on the bus as soon as it has one 128-byte read buffer. 1 = two: the 88sb2211 drives read data on the bus as soon as it has two 128-byte read buffers. 7 reserved_7 rw 0x0 reserved 9:8 mrlprftchmd rw 0x1 memory read line prefetch mode 0 = prefetch_disabled 1 = prefetch_enabled 2 = reserved 3 = aggressive_prefetch_enabled 10 mrlaggrinitwm rw 0x0 memory read line aggressive prefetch initial read watermark controls the number of 128-bytes buffers to be pre-fetched initially. note: relevant only if aggressive prefetch is enabled by the bit. 0 = two: the 88sb2211 pre-fetches two 128-bytes buffers initially. 1 = three: the 88sb2211 pre-fetches three 128-bytes buffers initially. table 102: reverse bridge prefetch and crs control register (continued) offset: 0x00080 bit field type/initval description
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 127 13:11 mrlaggrnextwm rw 0x0 memory read line aggressive prefetch next read watermark controls the criteria for issuing the next prefetch read request on the pci express interface. note: relevant only if aggressive prefetch is enabled by the bit. 0 = one data cycle: fetch next buffer after one data cycle is driven on the bus. 1 = two data cycles: fetch next buffer after two data cycles are driven on the bus. 2 = three data cycles: fetch next buffer after three data cycles are driven on the bus. 3 = four data cycles: fetch next buffer after four data cycles are driven on the bus. 4 = five data cycles: fetch next buffer af ter five data cycles are driven on the bus. 5 = six data cycles: fetch next buffer af ter six data cycles are driven on the bus. 6 = seven data cycles: fetch next buffer after seven data cycles are driven on the bus. 7 = eight data cycles: fetch next buffer after eight data cycles are driven on the bus. 14 mrlaggrreswm rw 0x0 memory read multiple aggressive prefetch response watermark controls the criteria for responding to the delayed read on the pci bus. note: relevant only if aggressive prefetch is enabled by the bit. 0 = one: the 88sb2211 drives read dat a on the bus as soon as it has one 128-byte read buffer. 1 = two: the 88sb2211 drives read data on the bus as soon as it has two 128-byte read buffers. 15 reserved_15 rw 0x0 reserved 17:16 mrprftchmd rw 0x0 memory read prefetch mode 0 = prefetch_disabled 1 = prefetch_enabled 2 = reserved 3 = aggressive_prefetch_enabled 18 mraggrinitwm rw 0x0 memory read aggressive prefetch initial read watermark controls the number of 128-bytes buffers to be pre-fetched initially. note: relevant only if aggressive prefetch is enabled by the bit. 0 = two: the 88sb2211 pre-fetches two 128-bytes buffers initially. 1 = three: the 88sb2211 pre-fetches three 128-bytes buffers initially. table 102: reverse bridge prefetch and crs control register (continued) offset: 0x00080 bit field type/initval description
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 128 document classification: proprietary information february 27, 2008, preliminary 21:19 mraggrnextwm rw 0x0 memory read aggressive prefetch next read watermark controls the criteria for issuing the next prefetch read request on the pci express interface. note: relevant only if aggressive prefetch is enabled by the bit. 0 = one data cycle: fetch next buffer after one data cycle is driven on the bus. 1 = two data cycles: fetch next buffer after two data cycles are driven on the bus. 2 = three data cycles: fetch next buffer after three data cycles are driven on the bus. 3 = four data cycles: fetch next buffer after four data cycles are driven on the bus. 4 = five data cycles: fetch next buffer af ter five data cycles are driven on the bus. 5 = six data cycles: fetch next buffer af ter six data cycles are driven on the bus. 6 = seven data cycles: fetch next buffer after seven data cycles are driven on the bus. 7 = eight data cycles: fetch next buffer after eight data cycles are driven on the bus. 22 mraggrreswm rw 0x0 memory read aggressive prefetch response watermark controls the criteria for responding to the delayed read on the pci bus. note: relevant only if aggressive prefetch is enabled by the bit. 0 = one: the 88sb2211 drives read dat a on the bus as soon as it has one 128-byte read buffer. 1 = two: the 88sb2211 drives read data on the bus as soon as it has two 128-byte read buffers. 23 reserved_23 rw 0x0 reserved 24 reserved_24 rw 0x1 reserved always write 1. 25 reserved_25 rw 0x1 reserved always write 1. 26 reserved_26 rw 0x0 reserved always write 0. 27 reserved_27 rw 0x0 reserved always write 0. 28 reserved_28 rw 0x0 reserved 29 reserved_29 rw 0x0 reserved table 102: reverse bridge prefetch and crs control register (continued) offset: 0x00080 bit field type/initval description
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 129 31:30 crsctrl rw 0x0 determines the 88sb2211 response when a pci-to-pci express configuration transaction is terminated with a configuration request retry status. 0 = crsrtry: retry configuration transactions on pci bus on every received crs. 1 = crsta: target-abort configurat ion transactions on pci bus on every received crs. 2 = crs1sec: retry configuration trans actions on pci bus from first received crs. target-abort configuration trans actions on pci bus 1 second after first received crs. 3 = crs8sec: retry configuration trans actions on pci bus from first received crs. target-abort configuration trans actions on pci bus 8 seconds after first received crs. table 102: reverse bridge prefetch and crs control register (continued) offset: 0x00080 bit field type/initval description table 103: marvell diagnostic pci express phy indirect access register offset: 0x000f4 bit field type/initval description 31:0 reserved rsvd 0x84cce5 reserved table 104: marvell diagnostic indirect address register offset: 0x000f8 bit field type/initval description 1:0 reserved rsvd 0x0 reserved 13:2 address rw 0x0 reserved note: for marvell usage only. 31:14 reserved_31_14 rsvd 0x0 reserved table 105: marvell diagnostic indirect data register offset: 0x000fc bit field type/initval description 31:0 data ro 0x0 reserved note: for marvell usage only.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 130 document classification: proprietary information february 27, 2008, preliminary a.4.3 reverse bridge mode ex tended configuration space table 106: pci express advanced error report header register offset: 0x00100 bit field type/initval description 15:0 pecapid ro 0x1 extended capability id the current value of this field id entifies the advanced error reporting capability. 19:16 capver ro 0x1 capability version 31:20 nextptr ro 0x0 next item pointer this field indicates the last item in the extended capabilities linked list. table 107: pci express uncorrectable error status register offset: 0x00104 bit field type/initval description 3:0 reserved rsvd 0x0 reserved 4 dlprterr rw1c 0x0 data link protocol error status 11:5 reserved rsvd 0x0 reserved 12 rpsntlperr rw1c 0x0 poisoned tlp status 13 fcprterr rw1c 0x0 flow control protocol error status set upon dllp update timeout (200s with no fc dllp received). 14 cmptoerr rw1c 0x0 completion timeout status 15 caerr rw1c 0x0 completer abort status 16 unexpcmperr rw1c 0x0 unexpected completion status 17 reserved rsvd 0x0 reserved
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 131 18 malftlperr rw1c 0x0 malformed tlp status 19 reserved rsvd 0x0 reserved 20 urerr rw1c 0x0 unsupported request error status 31:21 reserved rsvd 0x0 reserved table 107: pci express uncorrectable error status register (continued) offset: 0x00104 bit field type/initval description table 108: pci express uncorrectable error mask register offset: 0x00108 bit field type/initval description 3:0 reserved rsvd 0x0 reserved 4 dlprterrmsk rw 0x0 data link protocol error mask when an error is indicated in the pci express uncorrectable error status and the corresponding bit is set: - the header is not logged in the header log register - the first error pointer is not updated - an error message is not generated. the status bit is set regardless of the mask setting. 0 = not_masked 1 = masked 11:5 reserved rsvd 0x0 reserved 12 rpsntlperrmsk rw 0x0 poisoned tlp error mask 13 fcprterrmsk rw 0x0 flow control protocol error mask 14 cmptoerrmsk rw 0x0 completion timeout mask 15 caerrmsk rw 0x0 completer abort mask 16 unexpcmperrmsk rw 0x0 unexpected completion mask
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 132 document classification: proprietary information february 27, 2008, preliminary 17 reserved rsvd 0x0 reserved 18 malftlperrmsk rw 0x0 malformed tlp mask 19 reserved rsvd 0x0 reserved 20 urerrmsk rw 0x0 unsupported request error mask 31:21 reserved rsvd 0x0 reserved table 108: pci express uncorrectable error mask register (continued) offset: 0x00108 bit field type/initval description table 109: pci express uncorrectable error severity register offset: 0x0010c bit field type/initval description 3:0 reserved rsvd 0x1 reserved 4 dlprterrsev rw 0x1 data link protocol error severity controls the severity indication of the uncorrectable errors. each bit controls the error type of the corresponding bit in the pci express uncorrectable error status. 0 = non-fatal: error type is non-fatal. 1 = fatal: error type is fatal. 11:5 reserved rsvd 0x0 reserved 12 rpsntlperrsev rw 0x0 poisoned tlp error severity 13 fcprterrsev rw 0x1 flow control protocol error severity 14 cmptoerrsev rw 0x0 completion timeout severity 15 caersev rw 0x0 completer abort severity
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 133 16 unexpcmperrsev rw 0x0 unexpected completion severity 17 reserved rsvd 0x0 reserved 18 malftlperrsev rw 0x1 malformed tlp severity 19 reserved rsvd 0x0 reserved 20 urerrsev rw 0x0 unsupported request error severity 31:21 reserved rsvd 0x0 reserved table 109: pci express uncorrectable error severity register (continued) offset: 0x0010c bit field type/initval description table 110: pci express correctable error status register offset: 0x00110 bit field type/initval description 0 rcverr rw1c 0x0 receiver error status when set, this bit indicates that a receiver error has occurred. 5:1 reserved rsvd 0x0 reserved 6 badtlperr rw1c 0x0 bad tlp status 7 baddllperr rw1c 0x0 bad dllp status 8 rplyrllovrerr rw1c 0x0 replay number rollover status 11:9 reserved rsvd 0x0 reserved 12 rplytoerr rw1c 0x0 replay timer timeout status 31:13 reserved rsvd 0x0 reserved
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 134 document classification: proprietary information february 27, 2008, preliminary table 111: pci express correctable error mask register offset: 0x00114 bit field type/initval description 0 rcvmsk rw 0x0 receiver error mask if set, an error message is not generated upon occurrence of a receiver error. 0 = not_masked 1 = masked 5:1 reserved_5_1 rsvd 0x0 reserved 6 badtlpmsk rw 0x0 bad tlp mask 7 baddllperrmsk rw 0x0 bad dllp mask 8 rplyrllovrmsk rw 0x0 replay number rollover mask 11:9 reserved_11_9 rsvd 0x0 reserved 12 rplytomsk rw 0x0 replay timer timeout mask 13 advisorynonfatalerr or ro 0x0 advisory non-fatal error 31:14 reserved_31_14 rsvd 0x0 reserved
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 135 table 112: pci express advanced error capability and control register offset: 0x00118 bit field type/initval description 4:0 frsterrptr ro 0x0 first error pointer this field reports the bit position of t he first error reported in the pci express uncorrectable error status. this field locks upon receipt of the first uncorrectable error that is not masked. it remains locked until software clears it by writing 1 to the corresponding status bit. upon receipt of the next uncorrectable error that is not masked, the field locks again until cleared as described above. this lock and clear process continues to repeat itself. 4 = frsterrptr_4: data link protocol error 12 = frsterrptr_12: poisoned tlp error 13 = frsterrptr_13: flow control protocol error 14 = frsterrptr_14: completion timeout error 15 = frsterrptr_15: completer abort status 16 = frsterrptr_16: unexpected completion error 18 = frsterrptr_18: malformed tlp error 20 = frsterrptr_20: unsupported request error 31:5 reserved rsvd 0x0 reserved table 113: pci express header log first dword register offset: 0x0011c bit field type/initval description 31:0 hdrlog1dw ro 0x0 header log first dword logs the header of the first error reported in the pci express uncorrectable error status. this field locks upon receipt of the first uncorrectable error that is not masked. it remains locked until the software clears it by writing 1 to the corresponding status bit. upon receipt of the next uncorrectable error that is not masked, the field locks again until clear ed as described above. this lock and clear process continues to repeat itself. table 114: pci express header log second dword register offset: 0x00120 bit field type/initval description 31:0 hdrlog2dw ro 0x0 header log second dword
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 136 document classification: proprietary information february 27, 2008, preliminary table 115: pci express header log third dword register offset: 0x00124 bit field type/initval description 31:0 hdrlog3dw ro 0x0 header log third dword table 116: pci express header log fourth dword register offset: 0x00128 bit field type/initval description 31:0 hdrlog4dw ro 0x0 header log fourth dword table 117: pci uncorrectable error status register offset: 0x0012c bit field type/initval description 0 reserved_0 rsvd 0x0 target-abort on split completion status does not apply to conventional pci. 1 reserved_1 rsvd 0x0 master-abort on split completion status does not apply to conventional pci. 2 rcvta rw1c 0x0 received target-abort status 3 rcvma rw1c 0x0 received master-abort status 6:4 reserved_6_4 rsvd 0x0 reserved 7 ucdataerr rw1c 0x0 uncorrectable data error status 8 reserved_8 rsvd 0x0 uncorrectable attribute error status does not apply to conventional pci. 9 ucaddrerr rw1c 0x0 uncorrectable address error status
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 137 10 dtexp rw1c 0x0 delayed transaction discard timer expired status no header log. 11 perrdetected rw1c 0x0 pci_perrn assertion detected 12 serrdetected rw1c 0x0 pci_serrn assertion detected no header log. 13 internalbrerr rw1c 0x0 internal bridge error status no header log. 31:14 reserved_31_14 rsvd 0x0 reserved table 117: pci uncorrectable error status register (continued) offset: 0x0012c bit field type/initval description table 118: reverse bridge pci uncorrectable error mask register offset: 0x00130 bit field type/initval description 0 reserved_1_0 rsvd 0x0 reserved 1 reserved_1 rw 0x0 reserved 2 rcvtamsk rw 0x0 received target-abort mask status bit is set regardless of the mask setting. 0 = not_masked 1 = masked 3 rcvmamsk rw 0x1 received master-abort mask 4 reserved_4 rsvd 0x0 reserved 6:5 reserved_6_5 rw 0x1 reserved 7 ucdataerrmsk rw 0x1 uncorrectable data error mask
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 138 document classification: proprietary information february 27, 2008, preliminary 8 ucattrerrmsk rw 0x1 uncorrectable attribute error mask 9 ucaddrerrmsk rw 0x0 uncorrectable address error mask sar upon ep/rc mode. 10 dtexp rw 0x0 delayed transaction discard timer expired mask header in not logged. sar upon ep/rc mode. 11 perrdetectedmsk rw 0x0 pci_perrn assertion detected mask 12 serrdetectedmsk rw 0x1 pci_serrn assertion detected mask header in not logged. 13 internalbrerrmsk rw 0x0 internal bridge error mask no header log. 31:14 reserved_31_14 rsvd 0x0 reserved table 118: reverse bridge pci uncorrectable error mask register (continued) offset: 0x00130 bit field type/initval description table 119: pci uncorrectable error severity register offset: 0x00134 bit field type/initval description 0 reserved_1_0 rsvd 0x0 reserved 1 reserved_1 rw 0x0 reserved 2 rcvtasev rw 0x0 received target-abort severity controls the severity indication of the pci express secondary uncorrectable errors. each bit controls the error ty pe of the corresponding bit in the pci express secondary uncorr ectable error status. 0 = non-fatal: error type is non-fatal. 1 = fatal: error type is fatal. 3 rcvmasev rw 0x0 received master-abort severity
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 139 4 reserved_4 rsvd 0x0 reserved 6:5 reserved_6_5 rw 0x2 reserved 7 ucdataerrsev rw 0x0 uncorrectable data error severity 8 ucattrerrsev rw 0x1 uncorrectable attribute error severity 9 ucaddrerrsev rw 0x1 uncorrectable address error severity 10 dtexpsev rw 0x0 delayed transaction discar d timer expired severity 11 perrdetectedsev rw 0x0 pci_perrn assertion severity 12 serrdetectedsev rw 0x1 pci_serrn assertion severity 13 internalbrerrsev rw 0x0 internal bridge error severity 31:14 reserved_31_14 rsvd 0x0 reserved table 119: pci uncorrectable error severity register (continued) offset: 0x00134 bit field type/initval description table 120: pci error capability and control register offset: 0x00138 bit field type/initval description 4:0 secucfrsterrptr ro 0x0 pci uncorrectable first error pointer this field reports the bit position of t he first error reported in the pci express secondary uncorrectable error status. this field locks upon receipt of the first uncorrectable error that is not masked. it remains locked until software clears it by writing 1 to the corresponding status bit. upon receipt of the next uncorrectable error that is not masked, the field locks again until cleared as described above. this lock and clear process continues to repeat itself. note: the bits in this field are sticky bits--they are not initialized or modified by reset.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 140 document classification: proprietary information february 27, 2008, preliminary 31:5 reserved rsvd 0x0 reserved table 120: pci error capability and control register (continued) offset: 0x00138 bit field type/initval description table 121: pci header log first dword register offset: 0x0013c bit field type/initval description 31:0 shl_transattr ro 0x0 pci header log first dword logs the header of the first error reported in the pci express secondary uncorrectable error status. this field locks upon receipt of the first uncorrectable error that is not masked. it remains locked until software clears it by writing 1 to the corresponding status bit. upon receipt of the next uncorrectable error that is not masked, the field locks again until cleared as described above. this lock and clear process continues to repeat itself. transaction attribute the value transferred on ad[31:0] during the attribute phase. this field is not relevant to conventional pci. this field is hardwired to 0. table 122: pci header log second dword register offset: 0x00140 bit field type/initval description 3:0 shl_transattr ro 0x0 transaction attribute the value transferred on pci_cbe[3:0]n during the attribute phase. this field is not relevant to conventional pci. this field is hardwired to 0. 7:4 shl_transcmdlow ro 0x0 transaction command lower the 4-bit value transferred on pci_c be[3:0]n during the first address phase. 11:8 shl_transcmdup ro 0x0 transaction command upper the 4-bit value transferred on pci_cbe[3:0]n during the second address phase of a dac transaction. 31:12 reserved rsvd 0x0 reserved
88sb2211 register set reverse bridge mode configuration registers copyright ? 2008 marvell doc. no. mv-s104870-u0 rev. b february 27, 2008, preliminary document classification: proprietary information page 141 table 123: pci header log third dword register offset: 0x00144 bit field type/initval description 31:0 shl_addrlow ro 0x0 transaction address low. the 32-bit value transferred on ad[ 31:0] during the first address phase. table 124: pci header log fourth dword register offset: 0x00148 bit field type/initval description 31:0 shl_addrhigh ro 0x0 transaction address high. the 32-bit value transferred on ad[31:0] during the second address phase. in the case of a 32-bit address, this field is set to zero.
88sb2211 datasheet doc. no. mv-s104870-u0 rev. b copyright ? 2008 marvell page 142 document classification: proprietary information february 27, 2008, preliminary b revision history table 125: revision history document type revision date initial release a november 14, 2007 release b february 27, 2008 1. this document is now unrestricted. 2. figure 1, 88sb2211 interface pin logic diagram, on page 11 changed pci_clk_out[0]/pci_idseln from input to bi-directional. 3. updated table 15, power dissipation, on page 29 .
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